Datasheet
Intel® Xeon® Processor D-1500 Product Family 15
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.58 CEM—Correctable Error Mask Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................507
13.1.59 AECC—Advanced Error Capabilities and Control Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................507
13.1.60 RES—Root Error Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) . 508
13.1.61 PECR2—PCI Express* Configuration Register 2 (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................508
13.1.62 PEETM—PCI Express* Extended Test Mode Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................508
13.1.63 PEC1—PCI Express* Configuration Register 1 (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................509
14 High Precision Event Timer Registers.............................................................................511
14.1 Memory Mapped Registers .......................................................................................511
14.1.1 GCAP_ID—General Capabilities and Identification Register ................................512
14.1.2 GEN_CONF—General Configuration Register....................................................512
14.1.3 GINTR_STA—General Interrupt Status Register ...............................................513
14.1.4 MAIN_CNT—Main Counter Value Register .......................................................514
14.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register............................514
14.1.6 TIMn_COMP—Timer n Comparator Value Register ............................................516
14.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message Interrupt Rout
Register .....................................................................................................517
15 Serial Peripheral Interface (SPI) ...................................................................................519
15.1 Serial Peripheral Interface Memory Mapped Configuration Registers...............................519
15.1.1 BFPR –BIOS Flash Primary Region Register (SPI Memory Mapped
Configuration Registers)...............................................................................520
15.1.2 HSFS—Hardware Sequencing Flash Status Register (SPI Memory Mapped
Configuration Registers)...............................................................................521
15.1.3 HSFC—Hardware Sequencing Flash Control Register (SPI Memory Mapped
Configuration Registers)...............................................................................522
15.1.4 FADDR—Flash Address Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................522
15.1.5 FDATA0—Flash Data 0 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................523
15.1.6 FDATAN—Flash Data [N] Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................523
15.1.7 FRAP—Flash Regions Access Permissions Register (SPI Memory Mapped
Configuration Registers)...............................................................................523
15.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register (SPI Memory Mapped
Configuration Registers)...............................................................................524
15.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register (SPI Memory Mapped
Configuration Registers)...............................................................................524
15.1.10 FREG2—Flash Region 2 (Intel
®
ME) Register (SPI Memory Mapped
Configuration Registers)...............................................................................525
15.1.11 FREG3—Flash Region 3 (GbE) Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................525
15.1.12 FREG4—Flash Region 4 (Platform Data) Register (SPI Memory Mapped
Configuration Registers)...............................................................................525
15.1.13 PR0—Protected Range 0 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................526
15.1.14 PR1—Protected Range 1 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................526
15.1.15 PR2—Protected Range 2 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................526
15.1.16 PR3—Protected Range 3 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................527
15.1.17 PR4—Protected Range 4 Register (SPI Memory Mapped Configuration
Registers) ..................................................................................................527
15.1.18 SSFS—Software Sequencing Flash Status Register (SPI Memory Mapped
Configuration Registers)...............................................................................528
15.1.19 SSFC—Software Sequencing Flash Control Register (SPI Memory Mapped
Configuration Registers)...............................................................................528
15.1.20 PREOP—Prefix Opcode Configuration Register (SPI Memory Mapped
Configuration Registers)...............................................................................529
15.1.21 OPTYPE—Opcode Type Configuration Register (SPI Memory Mapped
Configuration Registers)...............................................................................530