Datasheet

Functional Description
148 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
When programmed for the Process Call command, Intel® Xeon® Processor D-1500
Product Family transmits the Transmit Slave Address, Host Command, DATA0 and
DATA1 registers. Data received from the device is stored in the DATA0 and DATA1
registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces
undefined results. Software must force either I2C_EN or PEC_EN to 0 when running
this command. See Section 5.5.6 of the System Management Bus (SMBus)
Specification, Version 2.0 for the format of the protocol.
Note: For process call command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, Offset 04h) needs to be 0.
Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code
(Bits 18:11 in the bit sequence) are not sent - as a result, the slave will not
acknowledge (Bit 19 in the sequence).
Block Read/Write
Intel® Xeon® Processor D-1500 Product Family contains a 32-byte buffer for read and
write data which can be enabled by setting bit 1 of the Auxiliary Control register at
offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is
filled with write data before transmission, and filled with read data on reception. In
Intel® Xeon® Processor D-1500 Product Family, the interrupt is generated only after a
transmission or reception of 32 bytes, or when the entire byte count has been
transmitted/received.
Note: When operating in I
2
C* mode (I2C_EN bit is set), Intel® Xeon® Processor D-1500
Product Family will never use the 32-byte buffer for any block commands.
The byte count field is transmitted but ignored by Intel® Xeon® Processor D-1500
Product Family as software will end the transfer after all bytes it cares about have been
sent or received.
For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and
AAC bits to 0 when running this command.
The block write begins with a slave address and a write condition. After the command
code Intel® Xeon® Processor D-1500 Product Family issues a byte count describing
how many more bytes will follow in the message. If a slave had 20 bytes to send, the
first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count
may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
Byte register; the total data sent being the value stored in the Data0 Register. On block
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register. See Section 5.5.7 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.
Intel® Xeon® Processor D-1500 Product Family will still send the number of bytes (on
writes) or receive the number of bytes (on reads) indicated in the DATA0 register.
However, it will not send the contents of the DATA0 register as part of the message.
Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in
the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in
the sequence).