Datasheet

Functional Description
146 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
different SMBus command protocols and is controlled by the host controller. Intel®
Xeon® Processor D-1500 Product Family’s SMBus controller logic is clocked by RTC
clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the Host Notify command (which is
actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done using the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
Intel® Xeon® Processor D-1500 Product Family SMBus host controller checks for parity
errors as a target. If an error is detected, the detected parity error bit in the PCI Status
Register (D31:F3:Offset 06h:Bit 15) is set. If Bit 6 and Bit 8 of the PCI Command
Register (D31:F3:Offset 04h) are set, an SERR# is generated and the signaled SERR#
bit in the PCI Status Register (bit 14) is set.
3.20.1 Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write,
Block
Write–Block Read Process Call,
and Host Notify.
The SMBus host controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMBus Host
controller performs the requested transaction, and interrupts the processor (or
generates an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control, Host Command,
Transmit Slave Address, Data 0, Data 1) should not be changed or read until the
interrupt status message (INTR) has been set (indicating the completion of the
command). Any register values needed for computation purposes should be saved prior
to issuing of a new command, as the SMBus host controller updates all registers while
completing the new command.
Intel® Xeon® Processor D-1500 Product Family supports the System Management Bus
(SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify
protocol, is available on the SMBus pins. The SMLink and SMBus signals can be tied
together externally depending on TCO mode used. Refer to Section 3.13.2 for more
details.
Using the SMB host controller to send commands to Intel® Xeon® Processor D-1500
Product Family SMB slave port is
not supported.