Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 145
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2. The Hub Controller provides the mechanism for host-to-hub communication. Hub-
specific status and control commands permit the host to configure a hub and to
monitor and control its individual downstream facing ports.
3. The Transaction Translator (TT) responds to high-speed split transactions and
translates them to full-/low-speed transactions with full-/low-speed devices
attached on downstream facing ports. There is 1 TT per RMH in Intel® Xeon®
Processor D-1500 Product Family.
See chapter 11 of the USB 2.0 Specification for more details on the architecture of the
hubs.
3.19 xHCI Controller (D20:F0)
Intel® Xeon® Processor D-1500 Product Family contains an eXtensible Host Controller
Interface (xHCI) host controller which supports up to 4 USB 2.0 ports of which up to 4
can be used as USB 3.0 ports with board routing, ACPI table and BIOS considerations.
This controller allows data transfers of up to 5 Gb/s. The controller supports
SuperSpeed (SS), high-speed (HS), full-speed (FS) and low speed (LS) traffic on the
bus.
The xHCI controller does not have a USB Debug port. If USB debug port functionality is
desired then the system SW must use the EHCI-based debug port discussed in
Section 3.17.9.
Note: Some USB 3.0 motherboard down devices do not require support for USB 2.0 speed
and it is possible to route only the SuperSpeed signals, as allowed by the USB 3.0
specification. In this special case, USB 2.0 and USB 3.0 signals will not need to be
paired together, thereby allowing support for more than 4 USB connections.
3.20 SMBus Controller (D31:F3)
Intel® Xeon® Processor D-1500 Product Family provides an System Management Bus
(SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller
provides a mechanism for the processor to initiate communications with SMBus
peripherals (slaves). Intel® Xeon® Processor D-1500 Product Family is also capable of
operating in a mode in which it can communicate with I
2
C compatible devices. The host
SMBus controller supports up to 100 KHz clock speed.
Intel® Xeon® Processor D-1500 Product Family can perform SMBus messages with
either packet error checking (PEC) enabled or disabled. The actual PEC calculation and
checking is performed in hardware by Intel® Xeon® Processor D-1500 Product Family.
The Slave Interface allows an external master to read from or write to Intel® Xeon®
Processor D-1500 Product Family. Write cycles can be used to cause certain events or
pass messages, and the read cycles can be used to determine the state of various
status bits. Intel® Xeon® Processor D-1500 Product Family’s internal host controller
cannot access Intel® Xeon® Processor D-1500 Product Family’s internal Slave
Interface.
Intel® Xeon® Processor D-1500 Product Family SMBus logic exists in D31:F3
configuration space, and consists of a transmit data path, and host controller. The
transmit data path provides the data flow logic needed to implement the seven