Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 143
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.17.12 Function Level Reset Support (FLR)
The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR
capability can be used in conjunction with Intel Virtualization Technology. FLR allows an
Operating System in a Virtual Machine to have complete control over a device,
including its initialization, without interfering with the rest of the platform. The device
provides a software interface that enables the Operating System to reset the whole
device as if a platform reset was asserted.
3.17.12.1 FLR Steps
3.17.12.1.1 FLR Initialization
1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.
2. All subsequent requests targeting the Function will not be claimed and will be
Master Abort Immediate on the bus. This includes any configuration, I/O or
Memory cycles, however, the Function shall continue to accept completions
targeting the Function.
3.17.12.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function
except those indicated otherwise and reset all internal states of the Function to the
default or initial condition.
3.17.12.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be
used to indicate to the software that the FLR reset is completed.
Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before
accessing the function.
3.17.13 USB Overcurrent Protection
Intel® Xeon® Processor D-1500 Product Family has implemented programmable USB
Overcurrent signals. Intel® Xeon® Processor D-1500 Product Family provides a total of
8 overcurrent pins to be shared across the 4 USB 2.0 and 4 USB 3.0 ports.
Each pin is mapped to one or more ports by setting bits in the Over-Current Map
registers, depending on whether the port is mapped to EHCI or XHCI. Please refer to
the following sections for more details:
1. EHCI (USB 2.0 Ports): Section 3.17.13, “USB Overcurrent Protection” .
2. XHCI (USB 2.0 Ports): Section 11.2.31, “U2OCM1 - XHCI USB2 Overcurrent
Mapping Register1 (USB xHCI—D20:F0)” .
3. XHCI (USB 2.0 Ports): Section 11.2.32, “U2OCM2 - XHCI USB2 Overcurrent
Mapping Register 2 (USB xHCI—D20:F0)” .
4. XHCI (USB 3.0 Ports): Section 11.2.33, “U3OCM1 - XHCI USB3 Overcurrent Pin
Mapping 1 (USB xHCI—D20:F0)” .
5. XHCI (USB 3.0 Ports): Section 11.2.34, “U3OCM2 - XHCI USB3 Overcurrent Pin
Mapping 2 (USB xHCI—D20:F0)” .