Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 137
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
1. The EHC hardware does not inherently consume any more power when it is in the
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
Since the Debug Port uses the same memory range, the Debug Port is only
operational when the EHC is in the D0 state.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
PME# signal is used to signal wake events, and so on.
5. When the Device Power State field is written to D0 from D3, an internal reset is
generated. See Section 3.17.1.3, “EHC Resets” for general rules on the effects of
this reset.
6. Attempts to write any other value into the Device Power State field other than 00b
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field.
3.17.7.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
• The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
• When in D0, the Pause feature (See Section 3.17.7.1) enables dynamic processor
low-power states to be entered.
• The PLL in the EHC is disabled when entering the S4/S5 states (core power turns
off).
• All core well logic is reset in the S4/S5 states.
3.17.8 USB 2.0 Legacy Keyboard Operation
Intel® Xeon® Processor D-1500 Product Family must support the possibility of a
keyboard downstream from either a full-speed/low-speed or a high-speed port. The
description of the legacy keyboard support is unchanged from USB 1.1.
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
3.17.9 USB 2.0 Based Debug Port
Intel® Xeon® Processor D-1500 Product Family supports the elimination of the legacy
COM ports by providing the ability for debugger software to interact with devices on a
USB 2.0 port.
High-level restrictions and features are:
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.