Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 135
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Intel® Xeon® Processor D-1500 Product Family always performs any currently-
pending debug port transaction at the beginning of a microframe, followed by any
pending periodic traffic for the current microframe. If there is time left in the
microframe, then the EHC performs any pending asynchronous traffic until the end of
the microframe (EOF1). The debug port traffic is only presented on Port 1 and Port 9,
while the other ports are idle during this time.
3.17.4 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
3.17.5 Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
Intel® Xeon® Processor D-1500 Product Family EHCI allows entrance to USB test
modes, as defined in the USB 2.0 specification, including Test J, Test Packet, and so on.
However, Intel® Xeon® Processor D-1500 Product Family Test Packet test mode
interpacket gap timing may not meet the USB 2.0 specification.
3.17.6 USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only Intel® Xeon® Processor D-1500 Product Family-specific
interrupt and error-reporting behavior is documented in this section. The EHCI
Interrupts section must be read first, followed by this section of the datasheet to fully
comprehend the EHC interrupt and error-reporting functionality.
• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer
Error can never occur on Intel® Xeon® Processor D-1500 Product Family.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
• Intel® Xeon® Processor D-1500 Product Family may assert the interrupts which
are based on the interrupt threshold as soon as the status for the last complete
transaction in the interrupt interval has been posted in the internal write buffers.
The requirement in the Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met
internally.
• Since Intel® Xeon® Processor D-1500 Product Family supports the 1024-element
Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds.
• Intel® Xeon® Processor D-1500 Product Family delivers interrupts using PIRQH#.
• Intel® Xeon® Processor D-1500 Product Family does not modify the CERR count
on an Interrupt IN when the “Do Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent