Datasheet

Functional Description
130 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.16 High Precision Event Timers (HPET)
This function provides a set of timers that can be used by the operating system. The
timers are defined such that the operating system may be able to assign specific timers
to be used directly by specific applications. Each timer can be configured to cause a
separate interrupt.
Intel® Xeon® Processor D-1500 Product Family provides eight timers. The timers are
implemented as a single counter, and each timer has its own comparator and value
register. The counter increases monotonically. Each individual timer can generate an
interrupt when the value in its value register matches the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system. It is not expected that the operating system
will move the location of these timers once it is set by the BIOS.
3.16.1 Timer Accuracy
The timers are accurate over any 1 ms period to within 0.05% of the time specified in
the timer resolution fields.
Within any 100 microsecond period, the timer reports a time that is up to two ticks too
early or too late. Each tick is less than or equal to 100 ns, so this represents an error of
less than 0.2%.
The timer is monotonic. It does not return the same value on two consecutive reads
(unless the counter has rolled over and reached the same value).
The main counter is clocked by the 14.31818 MHz clock. The accuracy of the main
counter is as accurate as the 14.31818 MHz clock.
3.16.2 Interrupt Mapping
Mapping Option #1 (Legacy Replacement Option)
In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the
mapping found in Tab l e 3- 38.
Note: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor interrupts messages.
Table 3-38. Legacy Replacement Routing
Timer 8259 Mapping APIC Mapping Comment
0 IRQ0 IRQ2 In this case, the 8254 timer will not
cause any interrupts
1 IRQ8 IRQ8 In this case, the RTC will not cause any
interrupts.
2 & 3 Per IRQ Routing
Field.
Per IRQ Routing Field
4, 5, 6, 7 not available not available