Datasheet
Intel® Xeon® Processor D-1500 Product Family 13
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.1.1 VID—Vendor Identification Register (SMBus—D31:F3)......................................465
12.1.2 DID—Device Identification Register (SMBus—D31:F3) ......................................465
12.1.3 PCICMD—PCI Command Register (SMBus—D31:F3).........................................466
12.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)...............................................466
12.1.5 RID—Revision Identification Register (SMBus—D31:F3)....................................467
12.1.6 PI—Programming Interface Register (SMBus—D31:F3).....................................467
12.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) ............................................467
12.1.8 BCC—Base Class Code Register (SMBus—D31:F3) ...........................................467
12.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 Register (SMBus—
D31:F3).....................................................................................................467
12.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1 Register (SMBus—
D31:F3).....................................................................................................468
12.1.11 SMB_BASE—SMBus Base Address Register (SMBus—D31:F3)............................468
12.1.12 SVID—Subsystem Vendor Identification Register (SMBus—D31:F2/F4) ............... 468
12.1.13 SID—Subsystem Identification Register (SMBus—D31:F2/F4)............................468
12.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) ..........................................469
12.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3)............................................469
12.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) ....................................469
12.2 SMBus I/O and Memory Mapped I/O Registers ............................................................469
12.2.1 HST_STS—Host Status Register (SMBus—D31:F3)...........................................470
12.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) .........................................471
12.2.3 HST_CMD—Host Command Register (SMBus—D31:F3).....................................472
12.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBus—D31:F3) .......................473
12.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) ............................................473
12.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) ............................................473
12.2.7 Host_BLOCK_dB—Host Block Data Byte Register (SMBus—D31:F3)....................474
12.2.8 PEC—Packet Error Check (PEC) Register (SMBus—D31:F3) ...............................474
12.2.9 RCV_SLVA—Receive Slave Address Register (SMBus—D31:F3)..........................474
12.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) ..............................475
12.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3).....................................475
12.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ....................................475
12.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus—D31:F3) .....................476
12.2.14 SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3) .......................476
12.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)..........................................476
12.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3)....................................477
12.2.17 NOTIFY_DADDR—Notify Device Address Register (SMBus—D31:F3) ...................477
12.2.18 NOTIFY_DLOW—Notify Data Low Byte Register (SMBus—D31:F3)......................478
12.2.19 NOTIFY_DHIGH—Notify Data High Byte Register (SMBus—D31:F3) ....................478
13 PCI Express* Configuration Registers............................................................................479
13.1 PCI Express* Configuration Registers (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ......479
13.1.1 VID—Vendor Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................481
13.1.2 DID—Device Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................481
13.1.3 PCICMD—PCI Command Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) 481
13.1.4 PCISTS—PCI Status Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...... 482
13.1.5 RID—Revision Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................483
13.1.6 PI—Programming Interface Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................483
13.1.7 SCC—Sub Class Code Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)....483
13.1.8 BCC—Base Class Code Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ..483
13.1.9 CLS—Cache Line Size Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7).... 483
13.1.10 PLT—Primary Latency Timer Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................484
13.1.11 HEADTYP—Header Type Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) 484
13.1.12 BNUM—Bus Number Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ..... 484
13.1.13 SLT—Secondary Latency Timer Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................484
13.1.14 IOBL—I/O Base and Limit Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................484
13.1.15 SSTS—Secondary Status Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................485
13.1.16 MBL—Memory Base and Limit Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7).....................................................................485