Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 123
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• D0 – Device is working and instantly available.
• D1 – Device enters when it receives a STANdBY IMMEDIATE command. Exit latency
from this state is in seconds
• D3 – From the SATA device’s perspective, no different than a D1 state, in that it is
entered using the STANdBY IMMEDIATE command. However, an ACPI method is
also called which will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings
to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than
10 ns
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to
10 ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA controller defines these states as sub-states of the device D0 state.
3.15.7.2 Power State Transitions
3.15.7.2.1 Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would
be most analogous to CLKRUN# (in power savings, not in mechanism), where the
interface can have power saved while no commands are pending. The SATA controller
defines PHY layer power management (as performed using primitives) as a driver
operation from the host side, and a device proprietary mechanism on the device side.
The SATA controller accepts device transition types, but does not issue any transitions
as a host. All received requests from a SATA device will be ACKed.
When an operation is performed to the SATA controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
3.15.7.2.2 Device D1, D3 States
These states are entered after some period of time when software has determined that
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANdBY IMMEDIATE” command.
3.15.7.2.3 Host Controller D3
HOT
State
After the interface and device have been put into a low power state, the SATA host
controller may be put into a low power state. This is performed using the PCI power
management registers in configuration space. There are two very important aspects to
note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the memory or I/O spaces will result in master abort.