Datasheet
12 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.37 FLR_NEXT—Function Level Reset Next Capability Pointer Register (USB
EHCI—D29:F0)........................................................................................... 406
10.1.38 FLR_CLV—Function Level Reset Capability Length and Version Register
(USB EHCI—D29:F0)................................................................................... 407
10.1.39 FLR_CTRL—Function Level Reset Control Register (USB EHCI—D29:F0) ............. 407
10.1.40 FLR_STS—Function Level Reset Status Register (USB EHCI—D29:F0) ................ 407
10.2 Memory-Mapped I/O Registers ................................................................................. 407
10.2.1 Host Controller Capability Registers............................................................... 408
10.2.2 Host Controller Operational Registers ............................................................ 410
10.2.3 USB 2.0-Based Debug Port Registers ............................................................. 420
11 xHCI Controller Registers (D20:F0) ............................................................................... 423
11.1 USB xHCI Configuration Registers (USB xHCI—D20:F0)............................................... 423
11.2 VID—Vendor Identification Register (USB xHCI—D20:F0) ............................................ 424
11.2.1 DID—Device Identification Register (USB xHCI—D20:F0) ................................. 424
11.2.2 PCICMD—PCI Command Register (USB xHCI—D20:F0) .................................... 424
11.2.3 PCISTS—PCI Status Register (USB xHCI—D20:F0) .......................................... 425
11.2.4 RID—Revision Identification Register (USB xHCI—D20:F0) ............................... 426
11.2.5 PI—Programming Interface Register (USB xHCI—D20:F0) ................................ 426
11.2.6 SCC—Sub Class Code Register (USB xHCI—D20:F0)........................................ 426
11.2.7 BCC—Base Class Code Register (USB xHCI—D20:F0)....................................... 426
11.2.8 PMLT—Primary Master Latency Timer Register (USB xHCI—D20:F0) .................. 427
11.2.9 HEADTYP—Header Type Register (USB xHCI—D20:F0)..................................... 427
11.2.10 MEM_BASE_L—Memory Base Address Low Register (USB xHCI—D20:F0) ........... 427
11.2.11 MEM_BASE_H—Memory Base Address High Register (USB xHCI—D20:F0).......... 427
11.2.12 SVID—USB xHCI Subsystem Vendor ID Register (USB xHCI—D20:F0) ............... 428
11.2.13 SID—USB xHCI Subsystem ID Register (USB xHCI—D20:F0)............................ 428
11.2.14 CAP_PTR—Capabilities Pointer Register (USB xHCI—D20:F0) ............................ 428
11.2.15 INT_LN—Interrupt Line Register (USB xHCI—D20:F0)...................................... 428
11.2.16 INT_PN—Interrupt Pin Register (USB xHCI—D20:F0) ....................................... 428
11.2.17 XHCC—xHC System Bus Configuration Register (USB xHCI—D20:F0)................. 429
11.2.18 XHCC2—xHC System Bus Configuration Register 2 (USB xHCI—D20:F0) ............ 429
11.2.19 SBRN—Serial Bus Release Number Register (USB xHCI—D20:F0)...................... 429
11.2.20 FL_ADJ—Frame Length Adjustment Register (USB xHCI—D20:F0)..................... 430
11.2.21 PWR_CAPID—PCI Power Management Capability ID Register (USB xHCI—
D20:F0) .................................................................................................... 430
11.2.22 NXT_PTR1—Next Item Pointer #1 Register (USB xHCI—D20:F0) ....................... 431
11.2.23 PWR_CAP—Power Management Capabilities Register (USB xHCI—D20:F0) ......... 431
11.2.24 PWR_CNTL_STS—Power Management Control / Status Register (USB xHCI—
D20:F0) .................................................................................................... 432
11.2.25 MSI_CAPID—Message Signaled Interrupt Capability ID Register (USB xHCI—
D20:F0) .................................................................................................... 432
11.2.26 NEXT_PTR2— Next Item Pointer Register #2 (USB xHCI—D20:F0) .................... 432
11.2.27 MSI_MCTL— MSI Message Control Register (USB xHCI—D20:F0) ...................... 433
11.2.28 MSI_LMAD—MSI Lower Message Address Register (USB xHCI—D20:F0)............. 433
11.2.29 MSI_UMAD—MSI Upper Message Address Register (USB xHCI—D20:F0) ............ 433
11.2.30 MSI_MD—MSI Message Data Register (USB xHCI—D20:F0).............................. 433
11.2.31 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1 (USB xHCI—D20:F0) ....... 434
11.2.32 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2 (USB xHCI—
D20:F0) .................................................................................................... 434
11.2.33 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1 (USB xHCI—D20:F0) ............. 435
11.2.34 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2 (USB xHCI—D20:F0) ............. 436
11.2.35 XUSB2PR —xHC USB 2.0 Port Routing Register (USB xHCI—D20:F0) ................. 436
11.2.36 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register (USB xHCI—D20:F0)........ 437
11.2.37 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register (USB xHCI—
D20:F0) .................................................................................................... 437
11.2.38 USB3PRM—USB 3.0 Port Routing Mask Register (USB xHCI—D20:F0) ................ 437
11.2.39 USB2PDO—xHCI USB Port Disable Override Register (USB xHCI—D20:F0).......... 438
11.2.40 USB3PDO - USB3 Port Disable Override (USB xHCI—D20:F0) ........................... 438
11.3 Memory-Mapped I/O Registers ................................................................................. 438
11.3.1 Host Controller Capability Registers............................................................... 439
11.3.2 Host Controller Operational Registers ............................................................ 442
11.3.3 Host Controller Runtime Registers................................................................. 458
11.3.4 Doorbell Registers....................................................................................... 462
12 SMBus Controller Registers (D31:F3) ............................................................................465
12.1 PCI Configuration Registers (SMBus—D31:F3) ............................................................ 465