Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 119
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.14.5.2 Serial Message Format
In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The
SIO is required to have its LED control pin in a high-Z state as well to allow Intel®
Xeon® Processor D-1500 Product Family to blink the LED (refer to the reference
diagram).
The three components of the serial message include the sync, data, and idle fields. The
sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state
(LED on) provides external hardware a known initial condition and a known pattern. In
case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a
clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling
logic to the encoded clock.
The data field is shifted out with the highest byte first (MSB). Within each byte, the
most significant bit is shifted first (MSb).
The idle field is enforced by the hardware and is at least 2 bit times long. The hardware
will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in
hardware prevents time-based counting in BIOS as the hardware is immediately ready
for the next serial code when the Go bit is cleared. The idle state is represented as a
high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state
will result in a final 0-1 transition on the output Manchester data. Two full bit times of
idle correspond to a count of 4 time intervals (the width of the time interval is
controlled by the DRS field).
The following waveform shows a 1-byte serial write with a data byte of 5Ah. The
internal clock and bit position are for reference purposes only. The Manchester D is the
resultant data generated and serialized onto the GPIO. Since the buffer is operating in
open-drain mode the transitions are from high-Z to 0 and back.
3.15 SATA Host Controller (D31:F2, F5)
The SATA function in Intel® Xeon® Processor D-1500 Product Family has three modes
of operation to support different operating system conditions. In the case of Native IDE
enabled operating systems, Intel® Xeon® Processor D-1500 Product Family uses two
controllers to enable all six ports of the bus. The first controller (Device 31: Function 2)
supports ports 0 – 3 and the second controller (Device 31: Function 5) supports ports 4
and 5. When using a legacy operating system, only one controller (Device 31: Function
2) is available that supports ports 0 – 3. In AHCI or RAID mode, only one controller
(Device 31: Function 2) is utilized enabling all six ports and the second controller
(Device 31: Function 5) shall be disabled.
Internal Clock
Manchester D
8-bit sync field
(1111_1110)
Bit 7 0123456
5A data byte
2 clk
idle