Datasheet

Functional Description
118 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
The anticipated usage model is that either Intel® Xeon® Processor D-1500 Product
Family or the SIO can drive a pin low to turn off an LED. In the case of the power LED,
the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to
turn on. In this state, Intel® Xeon® Processor D-1500 Product Family can blink the
LED by driving its corresponding pin low and subsequently tri-stating the buffer. The I/
O buffer should not drive a ‘1’ when configured for this functionality and should be
capable of sinking 24 mA of current.
An external optical sensing device can detect the on/off state of the LED. By externally
post-processing the information from the optical device, the serial bit stream can be
recovered. The hardware will supply a ‘sync’ byte before the actual data transmission
to allow external detection of the transmit frequency. The frequency of transmission
should be limited to 1 transition every 1 μs to ensure the detector can reliably sample
the on/off state of the LED. To allow flexibility in pull-up resistor values for power
optimization, the frequency of the transmission is programmable using the DRS field in
the GP_GB_CMDSTS register.
The serial bit stream is Manchester encoded. This choice of transmission ensures that a
transition will be seen on every clock. The 1 or 0 data is based on the transmission
happening during the high or low phase of the clock.
As the clock will be encoded within the data stream, hardware must ensure that the Z-
0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through
glitch-free logic are possible methods to meet the glitch-free requirement.
A simplified hardware/software register interface provides control and status
information to track the activity of this block. Software enabling the serial blink
capability should implement an algorithm referenced below to send the serialized
message on the enabled GPIO.
1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared.
This will ensure that the GPIO is idled and a previously requested message is still
not in progress.
2. Write the data to serialize into the GP_GB_DATA register.
3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit.
This may be accomplished using a single write.
The reference diagram shows the LEDs being powered from the suspend supply. By
providing a generic capability that can be used both in the main and the suspend power
planes maximum flexibility can be achieved. A key point to make is that Intel® Xeon®
Processor D-1500 Product Family will not unintentionally drive the LED control pin low
unless a serialization is in progress. System board connections utilizing this
serialization capability are required to use the same power plane controlling the LED as
Intel® Xeon® Processor D-1500 Product Family GPIO pin. Otherwise, Intel® Xeon®
Processor D-1500 Product Family GPIO may float low during the message and prevent
the LED from being controlled from the SIO. The hardware will only be serializing
messages when the core power well is powered and the processor is operational.
Care should be taken to prevent Intel® Xeon® Processor D-1500 Product Family from
driving an active ‘1’ on a pin sharing the serial LED capability. Since the SIO could be
driving the line to 0, having Intel® Xeon® Processor D-1500 Product Family drive a 1
would create a high current path. A recommendation to avoid this condition involves
choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be set first
before changing the direction of the pin to an output. This sequence ensures the open-
drain capability of the buffer is properly configured before enabling the pin as an
output.