Datasheet

Functional Description

Intel® Xeon® Processor D-1500 Product Family 117

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

• Offset 44h: GPI_IO_SEL3[95:64]

• Offset 48h: GP_LVL3[95:64]

• Offset 60h: GP_RST_SEL[31:0]

• Offset 64h: GP_RST_SEL2[63:32]

• Offset 68h: GP_RST_SEL3[95:64]

Note: All other GPIO registers not listed here are not to be locked by GLE.

Once these registers are locked down, they become Read-Only registers and any

software writes to these registers will have no effect. To unlock the registers, the GPIO

Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes

from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled.

Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.

This ensures that only BIOS can change the GPIO configuration. If the GLE bit is

cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is

triggered and these registers will continue to be locked down.

3.14.5 Serial POST Codes over GPIO

Intel® Xeon® Processor D-1500 Product Family adds the extended capability allowing

system software to serialize POST or other messages on GPIO. This capability negates

the requirement for dedicated diagnostic LEDs on the platform.

3.14.5.1 Theory of Operation

For Intel® Xeon® Processor D-1500 Product Family generation POST code serialization

logic will be shared with GPIO. These GPIOs will likely be shared with LED control

offered by the Super I/O (SIO) component. Figure 3-8 shows a likely configuration.

Figure 3-8. Serial Post over GPIO Reference Circuit

SIO

V_3P3_STBY

LED

Note: The pull-up value is based on the brightness required.

Intel Xeon

Processor D-

1500 Product

Family