Datasheet
Functional Description
116 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.14.1 Power Wells
Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some Intel® Xeon® Processor
D-1500 Product Family GPIOs may be connected to pins on devices that exist in the
core well. If these GPIOs are outputs, there is a danger that a loss of core power
(PCH_PWROK low) or a Power Button Override
event results in Intel® Xeon® Processor D-1500 Product Family driving a pin to a logic
1 to another device that is powered down.
3.14.2 SMI# SCI and NMI Routing
The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or
neither. A bit can be routed to either an SMI# or an SCI, but not both.
3.14.3 Triggering
GPIO[15:0] have “sticky” bits on the input. Refer to the GPE0_STS register and the
ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles,
Intel® Xeon® Processor D-1500 Product Family keeps the sticky status bit active. The
active level can be selected in the GP_INV register. This does not apply to
GPI_NMI_STS residing in GPIO I/O space.
If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the
signal only needs to be active for about 60 ns to be latched. In the S4–S5 states, the
GPI inputs are sampled at 32.768 kHz, and thus must be active for at least
61 microseconds to
be latched.
Note: GPIs that are in the core well are not capable of waking the system from sleep states
where the core well is not powered.
If the input signal is still active when the latch is cleared, it will again be set. Another
edge trigger is not required. This makes these signals “level” triggered inputs.
3.14.4 GPIO Registers Lockdown
The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE)
bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.
• Offset 00h: GPIO_USE_SEL[31:0]
• Offset 04h: GP_IO_SEL[31:0]
• Offset 0Ch: GP_LVL[31:0]
• Offset 28h: GPI_NMI_EN[15:0]
• Offset 2Ch: GPI_INV[31:0]
• Offset 30h: GPIO_USE_SEL2[63:32]
• Offset 34h: GPI_IO_SEL2[63:32]
• Offset 38h: GP_LVL2[63:32]
• Offset 40h: GPIO_USE_SEL3[95:64]