Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 113
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.13.1.1 Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor
fails to fetch the first instruction after reset, the TCO timer times out twice and Intel®
Xeon® Processor D-1500 Product Family asserts PLTRST#.
3.13.1.2 Handling an Intruder
Intel® Xeon® Processor D-1500 Product Family has an input signal, INTRUDER#, that
can be attached to a switch that is activated by the system’s case being open. This
input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer),
this will set the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the
TCO_CNT register can enable Intel® Xeon® Processor D-1500 Product Family to cause
an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the
S5 state by writing to the SLP_EN bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by
clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI
if the intruder function is not required.
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written
as a 1, then the INTRD_DET bit will go to a 0 when INTRUDER# input signal goes
inactive. This is slightly different than a classic sticky bit, since most sticky bits would
remain active indefinitely when the signal goes active and would immediately go
inactive when a 1 is written to the bit.
Note: The INTRD_DET bit resides in Intel® Xeon® Processor D-1500 Product Family’s RTC
well, and is set and cleared synchronously with the RTC clock. Thus, when software
attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much
as two RTC clocks (about 65 µs) delay before the bit is actually cleared. Also, the
INTRUDER# signal should be asserted for a minimum of 1 ms to ensure that the
INTRD_DET bit will be set.
Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there will not be further SMIs, since the
INTRD_SEL bits would select that no SMI# be generated.
3.13.1.3 Detecting Improper Flash Programming
Intel® Xeon® Processor D-1500 Product Family can detect the case where the BIOS
flash is not programmed. This results in the first instruction fetched to have a value of
FFh. If this occurs, Intel® Xeon® Processor D-1500 Product Family sets the BAD_BIOS
bit. The BIOS flash may reside in FWH or flash on the SPI bus.
3.13.1.4 Heartbeat and Event Reporting using SMLink/SMBus
Heartbeat and event reporting using SMLink/SMBus is no longer supported. The Intel
AMT logic in Intel® Xeon® Processor D-1500 Product Family can be programmed to
generate an interrupt to the Intel Management Engine (Intel ME) when an event
occurs. The Intel ME will poll the TCO registers to gather appropriate bits to send the
event message to the Gigabit Ethernet controller, if the Intel ME is programmed to do
so.