Datasheet

Functional Description
112 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. Intel® Xeon® Processor D-1500 Product Family drops this type of reset request if received while the system is in S4/S5.
2. Intel® Xeon® Processor D-1500 Product Family does not drop this type of reset request if received while system is in a
software-entered S4/S5 state. However, Intel® Xeon® Processor D-1500 Product Family will perform the reset without
executing the RESET_WARN protocol in these states.
3. Intel® Xeon® Processor D-1500 Product Family does not send warning message to processor, reset occurs without delay.
4. Trigger will result in Global Reset with power cycle if the acknowledge message is not received by
Intel® Xeon® Processor D-1500 Product Family.
5. Intel® Xeon® Processor D-1500 Product Family waits for enabled wake event to complete reset.
3.13 System Management (D31:F0)
Intel® Xeon® Processor D-1500 Product Family provides various functions to make a
system easier to manage and to lower the Total Cost of Ownership (TCO) of the
system. Features and functions can be augmented using external A/D converters and
GPIO, as well as an external microcontroller.
The following features and functions are supported by Intel® Xeon® Processor D-1500
Product Family:
• Processor present detection
— Detects if processor fails to fetch the first instruction after reset
• Various Error detection (such as ECC Errors) indicated by host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
• Detection of bad BIOS Flash (FWH or Flash on SPI) programming
— Detects if data on first read is FFh (indicates that BIOS flash is not
programmed)
Note: Voltage ID from the processor can be read using GPI signals.
3.13.1 Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality can be provided without the aid of an external microcontroller.
Intel Management Engine Triggered Global Reset No No Yes
Intel Management Engine Triggered Host Reset with
power down (host stays there)
No Yes (Note 5) No (Note 4)
PLTRST# Entry Time-out No No Yes
S4/5 Entry Timeout No No No Yes
PROCPWRGD Stuck Low No No Yes
Power Management Watchdog Timer No No No Yes
Intel Management Engine Hardware Uncorrectable Error No No No Yes
Table 3-35. Causes of Host and Global Resets (Sheet 2 of 2)
Trigger
Host Reset
without
Power
Cycle
1
Host Reset
with Power
Cycle
2
Global Reset
with Power
Cycle
3
Straight to S5
(Host Stays
there)