Datasheet

Functional Description
110 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
SRTCRST# is used to reset portions of the Intel Management Engine and should not be
connected to a jumper or button on the platform. The only time this signal gets
asserted (driven low in combination with RTCRST#) should be when the coin cell
battery is removed or not installed and the platform is in the G3 state. Pulling this
signal low independently (without RTCRST# also being driven low) may cause the
platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that
SRTCRST# not be pulled low in the S0 to
S5 states.
3.12.10 Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes.
Intel® Xeon® Processor D-1500 Product Family does not support burst modes.
3.12.10.1 APM Power Management
Intel® Xeon® Processor D-1500 Product Family has a timer that, when enabled by the
1MIN_EN bit in the SMI Control and Enable register, generates an SMI once per minute.
The SMI handler can check for system activity by reading the DEVTRAP_STS register. If
none of the system bits are set, the SMI handler can increment a software counter.
When the counter reaches a sufficient number of consecutive minutes with no activity,
the SMI handler can then put the system into a lower power state.
If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC, keyboard controller accesses, or audio functions on LPC.
3.12.11 Reset Behavior
When a reset is triggered, Intel® Xeon® Processor D-1500 Product Family will send a
warning message to the processor to allow the processor to attempt to complete any
outstanding memory cycles and put memory into a safe state before the platform is
reset. When the processor is ready, it will send an acknowledge message to Intel®
Xeon® Processor D-1500 Product Family. Once the message is received, Intel® Xeon®
Processor D-1500 Product Family asserts PLTRST#.
Intel® Xeon® Processor D-1500 Product Family does not require an acknowledge
message from the processor to trigger PLTRST#. A global reset will occur after 4
seconds if an acknowledge from the processor is not received.
A reset in which the host platform is reset and PLTRST# is asserted is called a Host
Reset or Host Partition Reset. Depending on the trigger, a host reset may also result in
power cycling (see Tab l e 3- 3 5 for details). If a host reset is triggered and Intel®
Xeon® Processor D-1500 Product Family times out before receiving an acknowledge
message from the processor, a Global Reset with power cycle will occur.