Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 109
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.9.5 SLP_WLAN# Pin Behavior
Intel® Xeon® Processor D-1500 Product Family controls the voltage rails into the
external wireless LAN PHY using the SLP_WLAN# pin.
• The wireless LAN PHY is always powered when the Host is running.
— SLP_WLAN#=’1’ whenever SLP_S3#=’1’.
• If Wake on Wireless LAN (WoWLAN) is required from S4/S5 states, the host BIOS
must set HOST_WLAN_PP_EN (RCBA+3318h bit 4).
• If ME has access to the Wireless LAN device
— The Wireless LAN device must always be powered as long as Intel ME is
powered. SLP_WLAN#=’1’ whenever SLP_A#=’1’.
— If Wake on Wireless LAN (WoWLAN) is required from Moff state, Intel ME will
configure SLP_WLAN#=’1’ in Sx/Moff.
Intel ME configuration of SLP_WLAN# in Sx/Moff is dependant on Intel ME power policy
configuration.
3.12.9.6 SUSPWRDNACK / SUSWARN# / GPIO30 Steady State Pin Behavior
The following tables summarize SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior.
Notes:
1. Intel® Xeon® Processor D-1500 Product Family will drive SPDA pin based on INtel ME power policy
configuration.
3.12.9.7 RTCRST# and SRTCRST#
RTCRST# is used to reset Intel® Xeon® Processor D-1500 Product Family registers in
the RTC Well to their default value. If a jumper is used on this pin, it should only be
pulled low when system is in the G3 state and then replaced to the default jumper
position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear
internal Intel® Xeon® Processor D-1500 Product Family registers accordingly. It is
imperative that this signal not be pulled low in the S0 to S5 states.
Table 3-33. SUSPWRDNACK / SUSWARN# / GPIO30 Pin Behavior
GPIO30
Setting
Pin Value in S0
Pin Value in Sx/
Moff
Pin Value in Sx/
M3
SUSPWRDNACK Native 0 Depends on ME
power package and
source (note 1)
0
SUSWARN# Native 1 1 (note 2) 1
GPIO30 IN High-Z High-Z High-Z
OUT Depends on
GPIO30 output
data value
Depends on GPIO30
output data value
Depends on GPIO30
output data value
Table 3-34. SUSPWRDNACK during Reset
PIC Reserved Bits Value Returned
Power Cycle Reset 0
Global Reset 0
Straight to S5 Intel® Xeon® Processor D-1500 Product Family initially drive
to ‘0’ and then drive per ME power policy configuration.