Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 107
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
It is required that the power associated with PCIe* have been valid for 99 ms prior to
PCH_PWROK assertion in order to comply with the 100 ms PCIe 2.0 specification on
PLTRST# de-assertion.
Note: SYS_RESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PCH_PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets and avoids improperly reporting
power failures.
3.12.9.4 SLP_LAN# Pin Behavior
Intel® Xeon® Processor D-1500 Product Family controls the voltage rails into the
external LAN PHY using the
SLP_LAN# pin.
• The LAN PHY is always powered when the Host & ME systems are running.
— SLP_LAN#=’1’ whenever SLP_S3#=’1’ or SLP_A#=’1’.
• If the LAN PHY is required by ME in Sx/Moff, ME must configure SLP_LAN#=’1’
irrespective of the power source and the destination power state. ME must be
powered at least once after G3 to configure this.
• If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_PP_EN
(B0:D31:F0:A2h bit 12).
• If the LAN PHY is required in Sx/Moff, the host BIOS must set SX_PP_EN
(B0:D31:F0:A2h bit 11).
• If the LAN PHY is not required if the source of power is battery, the host BIOS must
set DC_PP_DIS (B0:D31:F0:A2h bit 14).
Note: Intel ME configuration of SLP_LAN# in Sx/Moff is dependant on Intel ME power policy
configuration.
The flow chart below shows how a decision is made to drive SLP_LAN# every time its
policy needs to be evaluated.