Datasheet

Functional Description
106 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.9 System Power Supplies, Planes, and Signals
3.12.9.1 Power Plane Control with SLP_S3#,
SLP_S4#, SLP_A# and SLP_LAN#
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power
must be maintained to Intel® Xeon® Processor D-1500 Product Family suspend well,
and to any other circuits that need to generate Wake signals from the Suspend-to-RAM
state.
Cutting power to the core may be done using the power supply, or by external FETs on
the motherboard.
The SLP_S4# output signal can be used to cut power to the system core supply, as well
as power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done using the power supply, or by external FETs
on the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_A# output signal can be used to cut power to the Intel Management Engine and
SPI flash on a platform that supports the M3 state.
SLP_LAN# output signal can be used to cut power to the external Clarkville GbE PHY
device.
3.12.9.2 SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in Intel® Xeon® Processor D-1500 Product Family
provides a mechanism to fully cycle the power to the DRAM and/or detect if the power
is not cycled for a minimum time.
Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h Bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
3.12.9.3 PCH_PWROK Signal
When asserted, PCH_PWROK is an indication to Intel® Xeon® Processor D-1500
Product Family that its core well power rails are powered and stable. PCH_PWROK can
be driven asynchronously. When Intel® Xeon® Processor D-1500 Product Family
PCH_PWROK is low, Intel® Xeon® Processor D-1500 Product Family asynchronously
asserts PLTRST#. PCH_PWROK must not glitch, even if RSMRST# is low.
Table 3-32. Register Write Accesses in ALT Access Mode
I/O Address Register Write Value
08h DMA Status Register for Channels 0–3
D0h DMA Status Register for Channels 4–7