Datasheet

Functional Description
104 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Table 3-30. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
Restore Data Restore Data
I/O
Addr
# of
Rds
Access Data
I/O
Addr
# of
Rds
Access Data
00h 2 1 DMA Chan 0 base address low
byte
40h 7 1 Timer Counter 0 status, bits
[5:0]
2 DMA Chan 0 base address high
byte
2 Timer Counter 0 base count low
byte
01h 2 1 DMA Chan 0 base count low byte 3 Timer Counter 0 base count
high byte
2 DMA Chan 0 base count high byte 4 Timer Counter 1 base count low
byte
02h 2 1 DMA Chan 1 base address low
byte
5 Timer Counter 1 base count
high byte
2 DMA Chan 1 base address high
byte
6 Timer Counter 2 base count low
byte
03h 2 1 DMA Chan 1 base count low byte 7 Timer Counter 2 base count
high byte
2 DMA Chan 1 base count high byte 41h 1 Timer Counter 1 status, bits
[5:0]
04h 2 1 DMA Chan 2 base address low
byte
42h 1 Timer Counter 2 status, bits
[5:0]
2 DMA Chan 2 base address high
byte
70h 1 Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
05h 2 1 DMA Chan 2 base count low byte C4h 2 1 DMA Chan 5 base address low
byte
2 DMA Chan 2 base count high byte 2 DMA Chan 5 base address high
byte
06h 2 1 DMA Chan 3 base address low
byte
C6h 2 1 DMA Chan 5 base count low
byte
2 DMA Chan 3 base address high
byte
2 DMA Chan 5 base count high
byte
07h 2 1 DMA Chan 3 base count low byte C8h 2 1 DMA Chan 6 base address low
byte
2 DMA Chan 3 base count high byte 2 DMA Chan 6 base address high
byte
08h 6 1 DMA Chan 0–3 Command
2
CAh 2 1 DMA Chan 6 base count low
byte
2 DMA Chan 0–3 Request 2 DMA Chan 6 base count high
byte
3DMA Chan 0 Mode:
Bits(1:0) = 00
CCh 2 1 DMA Chan 7 base address low
byte
4DMA Chan 1 Mode:
Bits(1:0) = 01
2 DMA Chan 7 base address high
byte
5DMA Chan 2 Mode:
Bits(1:0) = 10
CEh 2 1 DMA Chan 7 base count low
byte
6 DMA Chan 3 Mode: Bits(1:0) =
11.
2 DMA Chan 7 base count high
byte