Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 103
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: A thermal trip event will:
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave
receiving message and not set due to SMBAlert
3.12.8 ALT Access Mode
Before entering a low power state, several registers from powered down parts may
need to be saved. In the majority of cases, this is not an issue, as registers have read
and write paths. However, several of the ISA compatible registers are either read only
or write only. To get data out of write-only registers, and to restore data into read-only
registers, Intel® Xeon® Processor D-1500 Product Family implements an ALT access
mode.
If the ALT access mode is entered and exited after reading the registers of Intel®
Xeon® Processor D-1500 Product Family timer (8254), the timer starts counting faster
(13.5 ms). The following steps listed below can cause problems:
1. BIOS enters ALT access mode for reading Intel® Xeon® Processor D-1500 Product
Family timer related registers.
2. BIOS exits ALT access mode.
3. BIOS continues through the execution of other needed steps and passes control to
the operating system.
After getting control in step #3, if the operating system does not reprogram the system
timer again, the timer ticks may be happening faster than expected. For example
Microsoft* MS-DOS* and its associated software assume that the system timer is
running at 54.6 ms and as a result the time-outs in the software may be happening
faster than expected.
Operating systems (such as Microsoft Windows* 98 and Windows* 2000) reprogram
the system timer and therefore do not encounter this problem.
For other operating systems (such as Microsoft MS-DOS*), the BIOS should restore the
timer back to 54.6 ms before passing control to the operating system. If the BIOS is
entering ALT access mode before entering the suspend state it is not necessary to
restore the timer contents after the exit from ALT access mode.
3.12.8.1 Write Only Registers with Read Paths in ALT Access Mode
The registers described in Tab l e 3- 30 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.