Datasheet

Functional Description
102 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.7.3 PME# (PCI Power Management Event)
The PME# signal comes from a PCI Express* device to request that the system be
restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event.
The event occurs when the PME# signal goes from high to low. No event is caused
when it goes from low
to high.
There is also an internal PME_B0 bit. This is separate from the external PME# signal
and can cause the same effect.
3.12.7.4 SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, Intel®
Xeon® Processor D-1500 Product Family attempts to perform a “graceful” reset, by
waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is
detected active, the reset occurs immediately; otherwise, the counter starts. If at any
point during the count the SMBus goes idle the reset occurs. If, however, the counter
expires and the SMBus is still active, a reset is forced upon the system even though
activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. If bit 3 of the CF9h I/O register is set, then SYS_RESET#
will result in a full power cycle reset.
3.12.7.5 THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and
Intel® Xeon® Processor D-1500 Product Family immediately transitions to an S5 state,
driving SLP_S3#, SLP_S4#, and setting the CTS bit. The transition looks like a power
button override.
When a THRMTRIP# event occurs, Intel® Xeon® Processor D-1500 Product Family will
power down immediately without following the normal S0 -> S5 path. Intel® Xeon®
Processor D-1500 Product Family will immediately drive SLP_S3#, and SLP_S4#after
sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as Intel® Xeon® Processor D-1500 Product
Family, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active,
and Intel® Xeon® Processor D-1500 Product Family is relying on state machine logic to
perform the power down, the state machine may not be working, and the system will
not power down.
Intel® Xeon® Processor D-1500 Product Family provides filtering for short low glitches
on the THRMTRIP# signal in
order to prevent erroneous system shut downs from noise. Glitches shorter than
25 nsec
are ignored.
During boot, THRMTRIP# is ignored until SLP_S3#, PCH_PWROK, and PLTRST# are all
‘1’. During entry into a powered-down state (due to S4, S5 entry, power cycle reset,
and so on) THRMTRIP# is ignored until either SLP_S3# = 0, or Intel® Xeon®
Processor D-1500 Product Family PCH_PWROK = 0, or SYS_PWROK = 0.