Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 101
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
this case, the transition to the G2/S5 state should not depend on any particular
response from the processor (such as, Messages), nor any similar dependency from
any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable using the
PWRBTN_LVL bit.
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when Intel® Xeon® Processor D-1500
Product Family is in a S0 state. If the PWRBTN# signal is asserted and held active when
the system is in a suspend state (S1–S5), the assertion causes a wake event. Once the
system has resumed to the S0 state, the 4-second timer starts.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional
Sleep button. It differs from the power button in that it only is a request to go from S0
to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the
Sleep
Button cannot.
Although Intel® Xeon® Processor D-1500 Product Family does not include a specific
signal designated as a Sleep Button, one of the GPIO signals can be used to create a
“Control Method” Sleep Button. See the Advanced Configuration and Power Interface,
Version 2.0b for implementation details.
3.12.7.2 RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.
Ta b l e 3- 2 9 shows when the wake event is generated or ignored in different states. If in
the G0/S0/Cx states, Intel® Xeon® Processor D-1500 Product Family generates an
interrupt based on RI# active, and the interrupt will be set up as a Break event.
Note: Filtering/Debounce on RI# will not be done in I
NTEL® XEON® PROCESSOR D-1500
P
RODUCT FAMILY. Can be in modem or external.
Table 3-29. Transitions Due to RI# Signal
Present State Event RI_EN Event
S0 RI# Active X Ignored
S1–S5 RI# Active 0
1
Ignored
Wake Event