Datasheet
Functional Description
100 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Intel® Xeon® Processor D-1500 Product Family monitors both Intel® Xeon®
Processor D-1500 Product Family PWROK and RSMRST# to detect for power failures. If
Intel® Xeon® Processor D-1500 Product Family PWROK goes low, the PWROK_FLR bit
is set. If RSMRST# goes low, PWR_FLR is set.
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
3.12.7 Event Input Signals and Their Usage
Intel® Xeon® Processor D-1500 Product Family has various input signals that trigger
specific events. This section describes those signals and how they should be used.
3.12.7.1 PWRBTN# (Power Button)
Intel® Xeon® Processor D-1500 Product Family PWRBTN# signal operates as a “Fixed
Power Button” as described in the Advanced Configuration and Power Interface,
Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state
transition descriptions are included in Tab l e 3- 28 . The transitions start as soon as the
PWRBTN# is pressed (but after the debounce logic), and does not depend on when the
Power Button is released.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to the following Power Button
Override Function section for further details.
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–
S4), even if Intel® Xeon® Processor D-1500 Product Family PWROK is not active. In
Table 3-27. Transitions Due to Power Failure
State at Power Failure AFTERG3_EN bit Transition When Power Returns
S0, S1 1
0
S5
S0
S4 1
0
S4
S0
S5 1
0
S5
S0
Table 3-28. Transitions Due to Power Button
Present
State
Event Transition/Action Comment
S0/Cx PWRBTN# goes low SMI or SCI generated
(depending on SCI_EN,
PWRBTN_EN and GLB_SMI_EN)
Software typically initiates a
Sleep state
S1–S5 PWRBTN# goes low Wake Event. Transitions to S0
state
Standard wakeup
G3 PWRBTN# pressed None No effect since no power
Not latched nor detected
S0–S4 PWRBTN# held low for
at least 4 consecutive
seconds
Unconditional transition to S5
state
No dependence on any
subsystem










