Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 61
Table 18. Processor FSB Source Synchronous Address Signal Routing Guidelines
Signal Names Total Trace Length
Address
Group #1
Address
Group #2
Transmission Line Type
Min
(inches)
Max
(inches)
Nominal
Impedance (Ω)
Width &
Spacing (mils)
A[16:3]# A[31:17]# Strip-line 0.50 6.5 55 ± 15% 4 & 8
REQ[4:0]# Strip-line 0.50 6.5 55 ± 15% 4 & 8
ADSTB#[0] ADSTB#[1] Strip-line 0.50 6.5 55 ± 15% 4 & 12
5.4.5. Intel Celeron M Processor and Intel 852GM Chipset GMCH FSB
Signal Package Lengths
Table 19 lists the preliminary package trace lengths of the Intel Celeron M Processor and the Intel
852GM chipset GMCH for the source synchronous data and address signals. The processor FSB
package signals within the same group are routed to the same package trace length, but the GMCH
package signals within the same group are not routed to the same package trace length. As a result of
this package length compensation is required for GMCH. Refer to Section 5.4.1 for length matching
constrains and Section 5.4.2 package length compensation for further details. The processor package
traces are routed as micro-strip lines with a nominal characteristic impedance of 55 Ω ± 15%.