Specification Update

Errata
Specification Update 31
AN41. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem: The IO_SMI bit in SMRAM’s location 7FA4H is set to 1 by the CPU to indicate a System
Management Interrupt (SMI) occurred as the result of executing an instruction that
reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:
• A non-I/O instruction.
• SMI is pending while a lower priority event interrupts
• A REP I/O read
• An I/O read that redirects to MWAIT.
• In systems supporting Intel® Virtualization Technology a fault in the middle of an
IO operation that causes a VM Exit
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status: For the steppings affected, see the Summary Tables of Changes
.
AN42. Erratum removed
AN43. Erratum removed.
AN44. Logical Processors May Not Detect Write-Back (WB) Memory Writes
Problem: Multiprocessor systems may use polling of memory semaphores to synchronize
software activity. Because of this erratum, if a logical processor is polling a WB
memory location while it is being updated by another logical processor, the update
may not be detected.
Implication: System may livelock due to polling loop and undetected semaphore change. Intel has
not observed this erratum on commercially available systems.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes
.
AN45. Erratum removed