Guide

Intel 852GM Platform Power Delivery Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 225
12.5.3.3. DDR SMRCOMP Resistive Compensation
The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer
characteristics to specific board and operation environment characteristics. Refer to the
RS – Intel
®
852GM GMCH Chipset Datasheet and Figure 124 for details on resistive compensation. The
SMRCOMP signal should be routed with as wide a trace as possible. It should be a minimum of 12 mils
wide and be isolated from other signals with a minimum of 10 mils spacing.
Figure 124. GMCH SMRCOMP Resistive Compensation
60.4
Ω
± 1%
+V2.5
60.4
Ω
± 1%
SMRCOMP
0.1 µ F
The GMCH’s system memory resistive compensation mechanism also requires the generation of
reference voltages to the SMVSWINGL and SMVSWINGH pins. The schematic for SMVSWINGL and
SMVSWINGH voltage generation is illustrated in Figure 125. Two resistive dividers with R1b = R2a =
150
Ω ± 1% and R1a = R2b = 604 Ω ± 1% generate the SMVSWINGL and SMVSWINGH voltages.
SMVSWINGL and SMVSWINGH components should be placed within 0.5 inches of their respective
pins and connected with a 15-mil wide trace. To avoid coupling with any other signals, maintain a
minimum of 25 mils of separation to other signals.
Figure 125. GMCH System Memory Reference Voltage Generation Circuit
R1a
604Ω +1%
R2a
150Ω +1%
+VCCSM
852GM
GMCH
SMVSWINGL
SMVSWINGL
SMVSWINGH
R1b
150Ω +1%
R2b
604Ω +1%
+VCCSM
SMVSWINGH
0.1 µF 0.1 µF