Datasheet

Functional Description
R
198 Datasheet
Table 43. Display Configuration Space
Panel Power Sequence Timing Parameters Name
Spec Name From To
Min Max Units
T1+T2 Vdd On to LVDS Active
Panel Vdd must be on for
a minimum time before the
LVDS data stream is
enabled.
0.1 Vdd LVDS Active 0 60 ms
T5 Backlight
LVDS data must be
enabled for a minimum
time before the backlight is
turned on.
LVDS
Active
Backlight on 200 ms
TX Backlight State
Backlight must be
disabled for a minimum
time before the LVDS data
stream is stopped.
Backlight
Off
LVDS off X X ms
T3 LVDS State
Data must be off for a
minimum time before the
panel VDD is turned off.
LVDS Off Start power
off
0 50 ms
T4 Power cycle Delay
When panel VDD is turned
from On to Off, a minimum
wait must be satisfied
before the panel VDD is
enabled again.
Power Off Power On
Sequence
Start
400 X ms
5.5.2.10 Back Light Inverter Control
The GMCH offers integrated PWM for TFT panel Backlight Inverter control. Other methods of
control are specified in the Common Panel Interface Specification, Version 1.6.
• PWM – based Backlight Brightness Control
• SMBus-based Backlight Brightness Control
• DBL (Display Brightness Link) –to- VDL (Video Data Link) Power Sequencing
5.5.2.11 Digital Display Channel – DVOB and DVOC
The GMCH has the capability to support additional digital display devices (e.g. TMDS
transmitter, LVDS transmitter or TV-out encoder) through its digital video output port. DVO B
and DVOC can each deliver a 165 MHz dot clock on their 12-bit interface or deliver a 330 MHz
dot clock on a combined 24-bit interface.