Datasheet

E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
9
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
2.0. PINOUT
2.1. Pinout and Pin Descriptions
2.1.1. PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY PINOUT
INCINCINCFLUSH#VCC2VCC3A10A6NC
ADSC#EADS#W/R#VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSA8A4A30
VCC2
DET#
PWT
HITM#BUSCHK#
BE0#BE2#BE4#BE6#SCYCA20A18A16A14A12A11A7A3
APD/C#HIT#A20M#BE1#BE3#BE5#BE7#CLKRESETA19A17A15A13A9A5A29A28
A25 A31
A26A22
VCC3 A24 A27
A21VSS
D/P#
A23
INTRVSS
R/S#
NMI
SMI#VSS
INITIGNNE#
PEN#VSS
FRCMC#
1
VSS
STPCLK#VSS
VSS
NC
VSS
TRST#
TMSVSS
TDOTDI
TCKVSS
PICD1
D0VSS
PICD0D2
PICCLKVSS
D3D1
D5D4
D7D6
DP0 D8 D12 DP1
D9 D10 D14 D17 D21
D11 D13 D16 D20
NC D15 D18 D22
VCC3
BREQHLDAADS#
VSSLOCK#
VCC2
SMIACT#
PCD
VSSPCHK#
PBREQ#APCHK#
VSSPBGNT#
PHITM#PRDY
VSSHOLD
PHIT#
WB/WT#
VSSBOFF#
BRDYC#NA#
VSSBRDY#
EWBE#KEN#
VSSAHOLD
CACHE#INV
VSSMI/O#
BP2BP3
VSSPM1BP1
PM0BP0FERR#
VSSIERR#
D63DP7
VSSD62
D61D60
VSSD59
D57D58
VSSD56
D55D53
DP6D51DP5
D54D52D49D46D42
D50D48D44D40D39
INCD47D45DP4D38D36
INCD43VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
D37D35D33DP3D30
D34D32D31D29D27
INC
D41
VCC2
D28
D25
D26
DP2
D23
D24
D19
VCC3
VCC3
NC
NC
VCC3
VSS
NCNC
BF1
BF0
VSS
VSS
VSS
NC
CPUTYP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Top Side View
VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2VCC2VCC2VCC2VCC2VCC3 VCC3 VCC3 VCC3 VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
NOTE:
1. The FRCMC# pin is not defined for Pentium
®
processor with MMX™ technology. Pin Y35 should be left as a "NC" or tied
to V
CC3
via an external pull-up resistor.
PP0008a
Figure 2. Pentium
®
Processor with MMX™ Technology SPGA and PPGA Package Pinout
(Top Side View)