Datasheet

E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
37
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Table 15. Pentium
®
Processor with MMX™ Technology AC Specifications for
66-MHz Bus Operation (Cont’d)
(See Table 10 for V
CC
and T
CASE
specifications, C
L
= 0 pF.)
Symbol Parameter Min Max Unit Figure Notes
(INIT, FLUSH#, BRDYC#,
BUSCHK#) Hold Time, Async.
(27)
t
42c
Reset Configuration Signals
(BRDYC#, BUSCHK#) Setup
Time, Async.
3.0 CLK To RESET falling edge
(27)
t
43a
BF0, BF1, CPUTYP Setup Time 1.0 ms 8 To RESET falling edge
(22)
t
43b
BF0, BF1, CPUTYP Hold Time 2.0 CLK To RESET falling edge
(22)
t
43c
APICEN, BE4# Setup Time 2.0 CLK To RESET falling edge
t
43d
APICEN, BE4# Hold Time 2.0 CLK To RESET falling edge
t
44
TCK Frequency 16.0 MHz
t
45
TCK Period 62.5 ns 4
t
46
TCK High Time 25.0 ns 4 2V
(1)
t
47
TCK Low Time 25.0 ns 4 0.8V
(1)
t
48
TCK Fall Time 5.0 ns 4 (2.0V–0.8V)
(1, 8, 9)
t
49
TCK Rise Time 5.0 ns 4 (0.8V–2.0V)
(1, 8, 9)
t
50
TRST# Pulse Width 40.0 ns 10 Asynchronous
(1)
t
51
TDI, TMS Setup Time 5.0 ns 9
(7)
t
52
TDI, TMS Hold Time 13.0 ns 9
(7)
t
53
TDO Valid Delay 2.5 20.0 ns 9
(8)
t
54
TDO Float Delay 25.0 ns 9
(1, 8)
t
55
All Non-Test Outputs Valid Delay 2.5 20.0 ns 9
(3, 8, 10)
t
56
All Non-Test Outputs Float Delay 25.0 ns 9
(1, 3, 8, 10)
t
57
All Non-Test Inputs Setup Time 5.0 ns 9
(3, 7, 10)
t
58
All Non-Test Inputs Hold Time 13.0 ns 9
(3, 7, 10)
APIC AC Specifications
t
60a
PICCLK Frequency 2.0 16.66 MHz 4
t
60b
PICCLK Period 60.0 500.0 ns 4
t
60c
PICCLK High Time 15.0 ns 4
t
60d
PICCLK Low Time 15.0 ns 4