Datasheet

E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
25
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Table 5. Input Pins
Name Active Level
Synchronous/
Asynchronous
Internal
Resistor Qualified
A20M#
(1)
Low Asynchronous
AHOLD High Synchronous
APICEN High Synchronous/RESET Pull-up
BF0 N/A Synchronous/RESET Pull-down
BF1 N/A Synchronous/RESET Pull-up
BOFF# Low Synchronous
BRDY# Low Synchronous Pull-up Bus State T2, T12, T2P
BRDYC# Low Synchronous Pull-up Bus State T2, T12, T2P
BUSCHK# Low Synchronous Pull-up BRDY#
CLK N/A
CPUTYP High Synchronous/RESET Pull-down
EADS# Low Synchronous
EWBE# Low Synchronous BRDY#
FLUSH# Low Asynchronous
HOLD High Synchronous
IGNNE#
(1)
Low Asynchronous
INIT High Asynchronous
INTR High Asynchronous
INV High Synchronous EADS#
LINT[1:0] High Asynchronous APICEN at RESET
KEN# Low Synchronous First BRDY#/NA#
NA# Low Synchronous Bus State T2, TD, T2P
NMI High Asynchronous
PEN# Low Synchronous BRDY#
PICCLK High Asynchronous Pull-up
R/S# N/A Asynchronous Pull-up
RESET High Asynchronous
SMI# Low Asynchronous Pull-up
STPCLK# Low Asynchronous Pull-up
TCK N/A Pull-up
TDI N/A Synchronous/TCK Pull-up TCK
TMS N/A Synchronous/TCK Pull-up TCK
TRST# Low Asynchronous Pull-up
WB/WT# N/A Synchronous First BRDY#/NA#
NOTES:
1. Undefined when the processor is configured as a Dual processor.