Datasheet
E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY
21
5/23/97 10:47 AM 24318502.DOC
INTEL CONFIDENTIAL
(until publication date)
Table 2. Quick Pin Reference (Cont’d)
Symbol Type Name and Function
PEN# I The parity enable input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If
this pin is sampled active in the clock a data parity error is detected, the Pentium
processor with MMX technology will latch the address and control signals of the
cycle with the parity error in the machine check registers. If, in addition, the
machine check enable bit in CR4 is set to “1”, the Pentium processor with MMX
technology will vector to the machine check exception before the beginning of the
next instruction.
PHIT# I/O Private hit is a hit indication used when two Pentium processors with MMX
technology are configured in dual processing mode, in order to maintain local
cache coherency. PHIT# should be left unconnected if only one Pentium
processor with MMX technology exists in a system.
PHITM# I/O Private modified hit is a hit on a modified cache line indication used when two
Pentium processors with MMX technology are configured in dual processing
mode, in order to maintain local cache coherency. PHITM# should be left
unconnected if only one Pentium processor with MMX technology exists in a
system.
PICCLK I The APIC interrupt controller serial data bus clock is driven into the
programmable interrupt controller clock input of the Pentium processor with
MMX technology.
This pin is 3.3V-tolerant-only on the Pentium processor with MMX technology.
Please refer to the
Pentium
®
Processor Family Developer’s Manual
(Order
Number 241428) for the CLK and PICCLK signal quality specification.
PICD0-1
[DPEN#]
[APICEN]
I/O Programmable interrupt controller data lines 0-1 of the Pentium processor with
MMX technology comprise the data portion of the APIC 3-wire bus. They are
open-drain outputs that require external pull-up resistors. These signals are
multiplexed with DPEN# and APICEN respectively.
PM/BP[1:0] O These pins function as part of the performance monitoring feature.
The breakpoint 1-0 pins are multiplexed with the performance monitoring 1-0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
PRDY O The probe ready output pin is provided for use with the Intel debug port. Please
refer to the
Pentium
®
Processor Family Developer’s Manual
(Order Number
241428) for more details.
PWT O The page write through pin reflects the state of the PWT bit in CR3, the page
directory entry, or the page table entry. The PWT pin is used to provide an
external write back indication on a page-by-page basis.
R/S# I The run/stop input is provided for use with the Intel debug port. Please refer to
the
Pentium
®
Processor Family Developer’s Manual
(Order Number 241428) for
more details.