Datasheet

PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E

5/23/97 10:47 AM 24318502.DOC

INTEL CONFIDENTIAL

(until publication date)

Table 2. Quick Pin Reference (Cont’d)

Symbol Type Name and Function

LINT0/INTR I If the APIC is enabled, this pin is local interrupt 0. If the APIC is disabled, this pin

is INTR.

LINT1/NMI I If the APIC is enabled, this pin is local interrupt 1. If the APIC is disabled, this pin

is NMI.

LOCK# O The bus lock pin indicates that the current bus cycle is locked. The Pentium

processor with MMX technology will not allow a bus hold when LOCK# is asserted

(but AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the

first locked bus cycle and goes inactive after the BRDY# is returned for the last

locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one clock

between back-to-back locked cycles.

M/IO# O The memory/input-output is one of the primary bus cycle definition pins. It is

driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes

between memory and I/O cycles.

NA# I An active next address input indicates that the external memory system is ready

to accept a new bus cycle although all data transfers for the current cycle have

not yet completed. The Pentium processor with MMX technology will issue ADS# for

a pending cycle two clocks after NA# is asserted. The Pentium processor with MMX

technology supports up to 2 outstanding bus cycles.

NMI/LINT1 I The non-maskable interrupt request signal indicates that an external non-maskable

interrupt has been generated.

If the local APIC is enabled, this pin becomes LINT1.

PBGNT# I/O Private bus grant is the grant line that is used when two Pentium processors with

MMX technology are configured in dual processing mode, in order to perform

private bus arbitration. PBGNT# should be left unconnected if only one Pentium

processor with MMX technology exists in a system.

PBREQ# I/O Private bus request is the request line that is used when two Pentium processor

with MMX technology are configured in dual processing mode, in order to perform

private bus arbitration. PBREQ# should be left unconnected if only one Pentium

processor with MMX technology exists in a system.

PCD O The page cache disable pin reflects the state of the PCD bit in CR3, the Page

Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an

external cacheability indication on a page by page basis.

PCHK# O The parity check output indicates the result of a parity check on a data read. It is

driven with parity status two clocks after BRDY# is returned. PCHK# remains low

one clock for each clock in which a parity error was detected. Parity is checked

only for the bytes on which valid data is returned.

When two Pentium processors with MMX technology are operating in dual

processing mode, PCHK# may be driven two or three clocks after BRDY# is

returned.