Datasheet

ManualsBrandsIntel Manualscomputer componentsFV8050366233

6/26/97 9:16 AM 24318504.DOC

INTEL CONFIDENTIAL

(until publication date)

June 1997 Order Number: 243185.004

Maximum Operating Frequency 166 MHz 200 MHz 233 MHz

iCOMP

Index 2.0 Rating 160 182 203

NOTE: Contact Intel Corporation for more information about iCOMP

Index 2.0 ratings.

Support for MMX™ Technology

Compatible with Large Software Base

 MS-DOS*, Windows*, OS/2*, UNIX*

32-Bit Processor with 64-Bit Data Bus

Superscalar Architecture

 Enhanced Pipelines

 Two Pipelined Integer Units

Capable of Two Instructions per

Clock

 Pipelined MMX Unit

 Pipelined Floating-Point Unit

Separate Code and Data Caches

 16-Kbyte Code, 16-Kbyte Write

Back Data

 MESI Cache Protocol

Advanced Design Features

 Deeper Write Buffers

 Enhanced Branch Prediction

Feature

 Virtual Mode Extensions

Enhanced CMOS Silicon Technology

4-Mbyte Pages for Increased TLB Hit

Rate

IEEE 1149.1 Boundary Scan

Dual Processing Configuration

Internal Error Detection Features

Multi-Processor Support

 Multiprocessor Instructions

 Support for Second Level Cache

On-Chip Local APIC Controller

 MP Interrupt Management

 8259 Compatible

Power Management Features

 System Management Mode

 Clock Control

Fractional Bus Operation

 233 MHz Core/66 MHz Bus

 200 MHz Core/66 MHz Bus

 166 MHz Core/66 MHz Bus

The Pentium

processor with MMX™ technology extends the Pentium processor family, providing performance

needed for mainstream desktop applications as well as for workstations. The Pentium processor with MMX

technology is compatible with the entire installed base of applications for MS-DOS*, Windows*, OS/2* and

UNIX*. The Pentium processor with MMX technology is the first microprocessor to support Intel MMX

technology. Furthermore, the Pentium processor with MMX technology superscalar architecture can execute two

instructions per clock cycle. Enhanced branch prediction and separate caches also increase performance. The

pipelined floating-point unit delivers workstation level performance. Separate code and data caches reduce

cache conflicts while remaining software transparent. The Pentium processor with MMX technology has

4.5 million transistors and is built on Intel's enhanced CMOS silicon technology.

The Pentium processor with MMX technology may contain design defects or errors known as errata that may

cause the product to deviate from published specifications. Current characterized errata are available on

request.

PENTIUM® PROCESSOR WITH

MMX™ TECHNOLOGY

Summary of content (51 pages)

PAGE 1
E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Maximum Operating Frequency iCOMP® Index 2.
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY CONTENTS PAGE PAGE 1.0. MICROPROCESSOR ARCHITECTURE OVERVIEW ....................................................... 3 2.2. Design Notes................................................13 1.1. Pentium® Processor Family Architecture....... 5 2.4. Pin Reference Tables...................................24 1.2. Pentium® Processor with MMX™ Technology..................................................... 7 2.5. Pin Grouping According to Function............27 1.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E • Improved Instruction Execution Time • Separate Code and Data Caches The Pentium® processor with MMX™ technology extends the Intel Pentium family of microprocessors. It is binary compatible with the 8086/88, 80286, Intel386™ DX, Intel386 SX, Intel486™ DX, Intel486 SX, Intel486 DX2 and Pentium processors 60/66/75/90/100/120/133/150/166/200.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY For a more detailed description of the Pentium processor family products, please refer to the Pentium® Processor Family Developer’s Manual (Order Number 241428). 1.1. Pentium® Processor Family Architecture The application instruction set of the Pentium processor family includes the complete Intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Control TLB Branch Prefetch Target Address Buffer DP Logic Code Cache 16 KBytes 128 Instruction Pointer Control ROM Prefetch Buffers Instruction Decode Branch Verif.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY easy system design. Through a private bus, the two Pentium processors arbitrate for the external bus and maintain cache coherency. Dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. In this document, in order to distinguish between two Pentium processors in dual processing mode, one processor will be designated as the "Primary" processor and the other as the "Dual" processor.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY The integration of the MMX pipeline with the integer pipeline is very similar to that of the floating-point pipeline. Under some circumstances, two MMX instructions or one integer and one MMX instruction can be paired and issued in one clock cycle to increase throughput. The enhanced pipeline is described in more detail in the Pentium® Processor Family Developer’s Manual (Order Number 241428). 1.2.5. DEEPER WRITE BUFFERS 1.3.
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E 2.0. 2.1. PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY PINOUT Pinout and Pin Descriptions PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY PINOUT 2.1.1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 1 AN AK AJ 7 8 9 10 11 12 13 14 15 16 FLUSH# VCC2 VCC2 VSS VSS PWT HITM# BUSCHK# BE0# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VCC2 VSS BE2# VCC2 VSS BE4# VCC2 VSS BE6# VCC2 VSS VCC3 VSS NC SCYC VCC3 VSS A20 VCC3 VSS A18 VCC3 VSS A16 VCC3 VSS A14 A10 VSS A12 A6 NC A8 A4 A11 VSS AM A30 A7 AL A3 VSS AK AP D/C# HIT# A20M# BE1# BE3# BE5# BE7# CLK RESET A19 A17 A15 A13 A9 A5 A29 A28
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E 2.1.2. PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY PIN CROSS-REFERENCE TABLE FOR PENTIUM® PROCESSOR WITH MMX™ Table 1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 1.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. When a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. Square brackets around a signal name indicate that the signal is defined only at RESET.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 2. Quick Pin Reference (Cont’d) Symbol BE7#–BE4# BE3#–BE0# Type Name and Function O I/O The byte enable pins are used to determine which bytes must be written to external memory or which bytes were requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-3).
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E Table 2. Quick Pin Reference (Cont’d) Symbol BUSCHK# Type Name and Function I The bus check input allows the system to signal an unsuccessful completion of a bus cycle. If this pin is sampled active, the Pentium processor with MMX technology will latch the address and control signals in the machine check registers. If, in addition, the MCE bit in CR4 is set, the Pentium processor with MMX technology will vector to the machine check exception.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function D/P# O The dual/primary processor indication. The Primary processor drives this pin low when it is driving the bus, otherwise it drives this pin high. D/P# is always driven. D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin is defined only on the Primary processor.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E Table 2. Quick Pin Reference (Cont’d) Symbol FLUSH# Type I Name and Function When asserted, the cache flush input forces the Pentium processor with MMX technology to write back all modified lines in the data cache and invalidate its internal caches. A Flush Acknowledge special cycle will be generated by the Pentium processor with MMX technology indicating completion of the write back and invalidation.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function IERR# O The internal error pin is used to indicate internal parity errors. If a parity error occurs on a read from an internal array, the Pentium processor with MMX technology will assert the IERR# pin for one clock and then shutdown. IGNNE# I This is the ignore numeric error input. This pin has no effect when the NE bit in CR0 is set to 1. When the CR0.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function LINT0/INTR I If the APIC is enabled, this pin is local interrupt 0. If the APIC is disabled, this pin is INTR. LINT1/NMI I If the APIC is enabled, this pin is local interrupt 1. If the APIC is disabled, this pin is NMI. LOCK# O The bus lock pin indicates that the current bus cycle is locked.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function PEN# I The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. If this pin is sampled active in the clock a data parity error is detected, the Pentium processor with MMX technology will latch the address and control signals of the cycle with the parity error in the machine check registers.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY E Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function RESET I RESET forces the Pentium processor with MMX technology to begin execution at a known state. All the Pentium processor with MMX technology internal caches will be invalidated upon the RESET. Modified lines in the data cache are not written back.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 2. Quick Pin Reference (Cont’d) Symbol Type Name and Function VSS I The Pentium processor with MMX technology has 53ground inputs. W/R# O Write/read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W/R# distinguishes between write and read cycles.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 2.4. Pin Reference Tables Table 4.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 5.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 6. Input/Output Pins Active Level Name (1) When Floated Qualified (when an input) Internal Resistor A31-A3 N/A Address Hold, Bus Hold, BOFF# EADS# AP N/A Address Hold, Bus Hold, BOFF# EADS# BE3#-BE0# Low Address Hold, Bus Hold, BOFF# RESET D63-D0 N/A Bus Hold, BOFF# BRDY# DP7-DP0 N/A Bus Hold, BOFF# BRDY# DPEN# low PICD0 N/A Pull-up PICD1 N/A Pull-down Pull-down (2) RESET Pull-up NOTES: 1.
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E 2.5. PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Pin Grouping According to Function Table 8 organizes the pins with respect to their function. Table 8.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 3.0. ELECTRICAL SPECIFICATIONS This section describes the electrical differences between the Pentium processor with MMX technology and the Pentium processor 133/150/166/200, as well as the AC and DC specifications of the Pentium processor with MMX technology. Pentium processor 133/150/166/200 designs can easily be converted to support the Pentium processor with MMX technology.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY specified at different voltages. See Table 10 for the specification. The display should show continuous sampling of the voltage line, at 20 mV/div, and 500 ns/div with the trigger point set to the center point of the range. Slowly move the trigger to the high and low ends of the specification, and verify that excursions beyond these limits are not observed. There are no allowances for crossing the high and low limits of the voltage specification.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 3.1.2.4. Private Bus When two Pentium processors with MMX technology are operating in dual processor mode, a "private bus" exists to arbitrate for the processor bus and maintain local cache coherency. The private bus consists of two pinout changes: 1. Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. 2. Ten output pins become I/O pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#, HITM#, HLDA, SCYC, BE#4.
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E 3.3. PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY DC Specifications Table 10 and Table 11 list the DC Specifications of the Pentium processor with MMX technology. Table 10. VCC and TCASE Specifications Symbol Parameter Min Nom 0 Max Unit 70 °C Notes TCASE Case Temperature VCC2 VCC2 Voltage 2.7 2.8 2.9 V Range = 2.8 ± 3.57% (1) VCC3 VCC3 Voltage 3.135 3.3 3.6 V Range = 3.3 –5%, +9.09% (1) NOTES: 1. See the VCC measurement specification section earlier in this chapter. Table 11. 3.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY NOTES: 1. This value should be used for power supply design. It was determined using a worst case instruction mix and maximum VCC. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes. Table 13. Power Dissipation Requirements for Thermal Design (Measured at VCC2=2.8V and VCC3=3.3V.) Parameter Active Power Typical 7.9 (5) 7.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 14.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 3.4. AC Specifications The AC specifications consist of output delays, input setup requirements and input hold requirements. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 15. Pentium® Processor with MMX™ Technology AC Specifications for 66-MHz Bus Operation (Cont’d) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol Parameter Min Max Unit Figure Notes 10.0 ns 6 (1) t7 ADS#, ADSC#, AP, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay t8a APCHK#, IERR#, FERR# Valid Delay 1.0 8.3 ns 5 (4) t8b PCHK# Valid Delay 1.0 7.0 ns 5 (4) t9a BREQ Valid Delay 1.0 8.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 15. Pentium® Processor with MMX™ Technology AC Specifications for 66-MHz Bus Operation (Cont’d) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol Parameter Min Max Unit Figure Notes t24b PEN# Setup Time 4.8 ns 7 t25a BUSCHK#, EWBE#, PEN# Hold Time 1.0 ns 7 t25b HOLD Hold Time 1.5 ns 7 t26 A20M#, INTR, STPCLK# Setup Time 5.0 ns 7 (12, 16) t27 A20M#, INTR, STPCLK# Hold Time 1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 15. Pentium® Processor with MMX™ Technology AC Specifications for 66-MHz Bus Operation (Cont’d) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol Parameter Min Max Unit Figure t42c t43a Notes (27) (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. 3.0 BF0, BF1, CPUTYP Setup Time 1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 15. Pentium® Processor with MMX™ Technology AC Specifications for 66-MHz Bus Operation (Cont’d) (See Table 10 for VCC and TCASE specifications, CL = 0 pF.) Symbol Parameter Min Max Unit Figure Notes t60e PICCLK Rise Time 0.15 2.5 ns 4 t60f PICCLK Fall Time 0.15 2.5 ns 4 t60g PICD0-1 Setup Time 3.0 ns 7 To PICCLK t60h PICD0-1 Hold Time 2.5 ns 7 To PICCLK t60i PICD0-1 Valid Delay (LtoH) 4.0 38.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 16. Pentium® Processor with MMX™ Technology Dual Processor Mode AC Specifications for 66-MHz Bus Operation (See Table 10 for VCC and TCASE assumptions.) Symbol Parameter Min Max Unit Figure Notes t80a PBREQ#, PBGNT#, PHIT# Flight Time 0.0 2.0 ns 5 (11, 24) t80b PHITM# Flight Time 0.0 1.8 ns 5 (11, 24) t83a A5-A31 Setup Time 3.7 ns 7 (18) t83b D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time 4.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 11. This is a flight time specification, that includes both flight time and clock skew. The flight time is the time from where the unloaded driver crosses 1.5V (50% of min VCC), to where the receiver crosses the 1.5V level (50% of min VCC). See Figure 11. The minimum flight time minus the clock skew must be greater than zero. 12. Setup time is required to guarantee recognition on a specific clock.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 1.5V Tx min. Tx max. Signal 1.5V VALID Tx = t6, t8, t9, t10, t11, t12, t60i, t60j, t80a, t89 Figure 5. Valid Delay Timings Tx = t7, t13; Ty = t6min, t12min Figure 6. Float Delay Timings Tx = t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g (to PICCLK),t81, t83 Ty = t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h (to PICCLK), t82, t84 Figure 7. Setup and Hold Timings 41 5/23/97 10:47 AM 24318502.
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PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Tt = t40, Tu = t41, Tv = t37, T w =t42, t43a, t43c, t87, Tx = t43b, t43d, t43f, t88, Ty = t38, t39, Tz = t36 Figure 8. Reset and Configuration Timings Tr = t57, Ts = t58, Tu = t54, Tv = t51, Tw = t52, Tx = t53, Ty = t55, Tz = t56 Figure 9. Test Timings Tx = t50 Figure 10. Test Reset Timings 42 5/23/97 10:47 AM 24318502.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Figure 11. 50 Percent VCC Measurement of Flight Time 4.0. MECHANICAL SPECIFICATIONS The Pentium processor with MMX technology is packaged in 296-pin staggered pin grid array ceramic (SPGA) or plastic (PPGA) packages. The pins are arranged in a 37 x 37 matrix and the package dimensions are 1.95" x 1.95" (Table 17). A 1.25" x 1.25" copper tungsten heat spreader may be attached to the top of some of the ceramic packages.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY D D1 SEATING PLANE S1 L e1 S1 1.65 REF. D1 D ∅B Pin C3 A A1 A2 2.29 REF. 1.52 45° INDEX CHAMFER (INDEX CORNER) Figure 12. SPGA Package Dimensions Table 18. SPGA Package Dimensions Millimeters Symbol Min Max A 2.62 2.97 A1 0.69 0.84 A2 3.31 3.81 Inches Notes Min Max 0.103 0.117 Ceramic Lid 0.027 0.033 Ceramic Lid Ceramic Lid 0.130 0.150 Ceramic Lid B 0.43 0.51 0.017 0.020 D 49.28 49.78 1.940 1.960 D1 45.59 45.85 1.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Figure 13. PPGA Package Dimensions Table 19. PPGA Package Dimensions Millimeters Symbol Min Max A 2.72 A1 1.83 A2 Inches Notes Min Max 3.33 0.107 0.131 2.23 0.072 0.088 1.00 0.039 B 0.40 0.51 0.016 0.020 D 49.43 49.63 1.946 1.954 D1 45.59 45.85 1.795 1.805 D2 23.44 23.95 0.923 0.943 e1 2.29 2.79 0.090 0.110 F1 17.56 0.692 F2 23.04 0.907 L N 3.05 3.30 296 Notes 0.120 Lead Count 0.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 19. PPGA Package Dimensions Millimeters Symbol Min Max S1 1.52 2.54 5.0. Inches Notes 5.1.1. THERMAL SPECIFICATIONS The Pentium processor with MMX technology is specified for proper operation when case temperature, TCASE, (TC) is within the specified range of 0°C to 70°C. 5.1. Max 0.060 0.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY PPGA SPGA Figure 14. Technique fore Measuring TC on PPGA and SPGA Packages 47 5/23/97 10:47 AM 24318502.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 20. Thermal Resistance for SPGA Packages Heatsink Height θJC θCA (°C/Watt) vs. Laminar Airflow (linear ft/min) (inches) (°C/Watt) 0 100 200 400 600 800 0.25 0.9 9.2 8.1 6.7 4.6 3.7 3.1 0.35 0.9 8.9 7.6 6.1 4.1 3.4 2.9 0.45 0.9 8.5 7.1 5.4 3.7 3.0 2.6 0.55 0.9 8.2 6.6 4.8 3.3 2.7 2.4 0.65 0.9 7.8 6.1 4.4 3.1 2.5 2.2 0.80 0.9 7.1 5.4 4.0 2.9 2.3 2.1 1.00 0.9 6.4 4.8 3.7 2.7 2.2 1.9 1.20 0.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 10 Air Flow Rate [LFM] 9 0 200 600 8 Theta ca [C/W] 7 100 400 800 6 5 4 3 2 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Heat Sink Height [in] Figure 15. Thermal Resistance vs. Heatsink Height, SPGA Packages 49 5/23/97 10:47 AM 24318502.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY Table 21. Thermal Resistances for PPGA Packages Heat Sink Height θJC θCA (°C/Watt) vs. Laminar Airflow (linear ft/min) (inches) (°C/Watt) 0 100 200 400 600 800 0.25 0.4 8.9 7.8 6.4 4.3 3.4 2.8 0.35 0.4 8.6 7.3 5.8 3.8 3.1 2.6 0.45 0.4 8.2 6.8 5.1 3.4 2.7 2.3 0.55 0.4 7.9 6.3 4.5 3.0 2.4 2.1 0.65 0.4 7.5 5.8 4.1 2.8 2.2 1.9 0.80 0.4 6.8 5.1 3.7 2.6 2.0 1.8 1.00 0.4 6.1 4.5 3.4 2.4 1.9 1.6 1.20 0.
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E PENTIUM® PROCESSOR WITH MMX™ TECHNOLOGY 10 Air Flow Rate [LFM] 9 0 200 600 8 Theta ca [C/W] 7 100 400 800 6 5 4 3 2 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Heat Sink Height [in] Figure 16. Thermal Resistance vs. Heatsink Height, PPGA Packages 51 5/23/97 10:47 AM 24318502.