Datasheet
8 Datasheet, Volume 1
4-6 Processor Graphics Controller States ........................................................................ 45
4-7 G, S, and C State Combinations............................................................................... 45
4-8 D, S, and C State Combination ................................................................................ 46
4-9 Coordination of Thread Power States at the Core Level ............................................... 48
4-10 P_LVLx to MWAIT Conversion .................................................................................. 48
4-11 Coordination of Core Power States at the Package Level.............................................. 51
4-12 Targeted Memory State Conditions........................................................................... 56
5-1 Thermal Design Power (TDP) Specifications ............................................................... 65
5-2 Junction Temperature Specification .......................................................................... 65
5-3 Package Turbo Parameters...................................................................................... 65
5-4 Idle Power Specifications ........................................................................................ 67
6-1 Signal Description Buffer Types ............................................................................... 75
6-2 Memory Channel A Signals...................................................................................... 76
6-3 Memory Channel B Signals...................................................................................... 77
6-4 Memory Reference and Compensation ...................................................................... 77
6-5 Reset and Miscellaneous Signals .............................................................................. 78
6-6 PCI Express* Graphics Interface Signals ................................................................... 79
6-7 Embedded DisplayPort* Signals ............................................................................... 79
6-8 Intel
®
Flexible Display Interface (Intel
®
FDI) ............................................................ 80
6-9 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface....................... 80
6-10 Phase Lock Loop (PLL) Signals................................................................................. 80
6-11 Test Access Points (TAP) Signals.............................................................................. 81
6-12 Error and Thermal Protection Signals........................................................................ 81
6-13 Power Sequencing Signals ...................................................................................... 82
6-14 Processor Power Signals ......................................................................................... 82
6-15 Sense Signals ....................................................................................................... 83
6-16 Ground and Non-Critical to Function (NCTF) Signals ................................................... 83
6-17 Future Compatibility Signals.................................................................................... 84
6-18 Processor Internal Pull-Up / Pull-Down Resistors ........................................................ 84
7-1 IMVP7 Voltage Identification Definition ..................................................................... 87
7-2 VCCSA_VID configuration ....................................................................................... 90
7-3 Signal Groups1...................................................................................................... 91
7-4 Storage Condition Ratings....................................................................................... 94
7-5 Processor Core (V
CC
) Active and Idle Mode DC Voltage and Current Specifications .......... 95
7-6 Processor Uncore (V
CCIO
) Supply DC Voltage and Current Specifications........................ 96
7-7 Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications....................... 97
7-8 System Agent (V
CCSA
) Supply DC Voltage and Current Specifications ............................ 97
7-9 Processor PLL (V
CCPLL
) Supply DC Voltage and Current Specifications ........................... 97
7-10 Processor Graphics (VAXG) Supply DC Voltage and Current Specifications ..................... 98
7-11 DDR3 Signal Group DC Specifications ....................................................................... 99
7-12 Control Sideband and TAP Signal Group DC Specifications ..........................................100
7-13 PCI Express* DC Specifications...............................................................................100
7-14 Embedded DisplayPort* DC Specifications ................................................................101
7-15 PECI DC Electrical Limits........................................................................................102
8-1 rPGA988B Processor Pin List by Pin Name ................................................................110
8-2 BGA1224 Processor Ball List by Ball Name................................................................125
8-3 BGA1023 Processor Ball List by Ball Name................................................................144
9-1 DDR Data Swizzling Table – Channel A ....................................................................168
9-2 DDR Data Swizzling Table – Channel B ....................................................................169