Datasheet

6 Datasheet, Volume 1
6.5 Embedded DisplayPort* (eDP) Signals ................................................................. 79
6.6 Intel
®
Flexible Display Interface (Intel
®
FDI) Signals............................................. 80
6.7 Direct Media Interface (DMI) Signals ................................................................... 80
6.8 Phase Lock Loop (PLL) Signals ............................................................................ 80
6.9 Test Access Points (TAP) Signals ......................................................................... 81
6.10 Error and Thermal Protection Signals................................................................... 81
6.11 Power Sequencing Signals.................................................................................. 82
6.12 Processor Power Signals .................................................................................... 82
6.13 Sense Signals................................................................................................... 83
6.14 Ground and Non-Critical to Function (NCTF) Signals .............................................. 83
6.15 Future Compatibility Signals ............................................................................... 84
6.16 Processor Internal Pull-Up / Pull-Down Resistors ................................................... 84
7 Electrical Specifications .......................................................................................... 85
7.1 Power and Ground Pins...................................................................................... 85
7.2 Decoupling Guidelines ....................................................................................... 85
7.2.1 Voltage Rail Decoupling .......................................................................... 85
7.2.2 PLL Power Supply .................................................................................. 85
7.3 Voltage Identification (VID)................................................................................ 86
7.4 System Agent (SA) V
CC
VID ............................................................................... 90
7.5 Reserved or Unused Signals ............................................................................... 90
7.6 Signal Groups................................................................................................... 91
7.7 Test Access Port (TAP) Connection ...................................................................... 93
7.8 Storage Condition Specifications ......................................................................... 93
7.9 DC Specifications .............................................................................................. 94
7.9.1 Voltage and Current Specifications ........................................................... 95
7.10 Platform Environmental Control Interface (PECI) DC Specifications .........................101
7.10.1 PECI Bus Architecture............................................................................101
7.10.2 PECI DC Characteristics .........................................................................102
7.10.3 Input Device Hysteresis .........................................................................103
8 Processor Pin and Signal Information ....................................................................105
8.1 Processor Pin Assignments ................................................................................105
8.2 Package Mechanical Information ........................................................................155
9 DDR Data Swizzling................................................................................................167