Datasheet

Datasheet, Volume 1 3
Contents
1 Introduction ............................................................................................................ 11
1.1 Processor Feature Details ................................................................................... 13
1.1.1 Supported Technologies .......................................................................... 13
1.2 Interfaces ........................................................................................................ 13
1.2.1 System Memory Support ......................................................................... 13
1.2.2 PCI Express* ......................................................................................... 14
1.2.3 Direct Media Interface (DMI).................................................................... 15
1.2.4 Platform Environment Control Interface (PECI) ........................................... 16
1.2.5 Processor Graphics ................................................................................. 16
1.2.6 Embedded DisplayPort* (eDP).................................................................. 17
1.2.7 Intel
®
Flexible Display Interface (Intel
®
FDI) ............................................. 17
1.3 Power Management Support ............................................................................... 17
1.3.1 Processor Core....................................................................................... 17
1.3.2 System ................................................................................................. 17
1.3.3 Memory Controller.................................................................................. 17
1.3.4 PCI Express* ......................................................................................... 17
1.3.5 Direct Media Interface (DMI).................................................................... 17
1.3.6 Processor Graphics Controller...................................................................18
1.4 Thermal Management Support ............................................................................ 18
1.5 Package ........................................................................................................... 18
1.6 Terminology ..................................................................................................... 18
1.7 Related Documents............................................................................................ 20
2 Interfaces................................................................................................................ 21
2.1 System Memory Interface................................................................................... 21
2.1.1 System Memory Technology Supported ..................................................... 21
2.1.2 System Memory Timing Support............................................................... 22
2.1.3 System Memory Organization Modes......................................................... 22
2.1.3.1 Single-Channel Mode................................................................. 22
2.1.3.2 Dual-Channel Mode – Intel
®
Flex Memory Technology Mode ........... 22
2.1.4 Rules for Populating Memory Slots ............................................................ 23
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA)..........24
2.1.5.1 Just-in-Time Command Scheduling.............................................. 24
2.1.5.2 Command Overlap .................................................................... 24
2.1.5.3 Out-of-Order Scheduling ............................................................ 24
2.1.6 Memory Type Range Registers (MTRRs) Enhancement................................. 24
2.1.7 Data Scrambling .................................................................................... 24
2.1.8 DRAM Clock Generation........................................................................... 24
2.2 PCI Express* Interface....................................................................................... 25
2.2.1 PCI Express* Architecture ....................................................................... 25
2.2.1.1 Transaction Layer ..................................................................... 26
2.2.1.2 Data Link Layer ........................................................................ 26
2.2.1.3 Physical Layer .......................................................................... 26
2.2.2 PCI Express* Configuration Mechanism ..................................................... 27
2.2.3 PCI Express Graphics .............................................................................. 27
2.2.4 PCI Express* Lanes Connection ................................................................ 28
2.3 Direct Media Interface (DMI)............................................................................... 28
2.3.1 DMI Error Flow....................................................................................... 28
2.3.2 Processor / PCH Compatibility Assumptions................................................ 28
2.3.3 DMI Link Down ...................................................................................... 29
2.4 Processor Graphics Controller (GT) ...................................................................... 29