Datasheet

Land Listing and Signal Description
72 Datasheet
RESET# I
Asserting the RESET# signal resets all processors to
known states and invalidates their internal caches without
writing back any of their contents. For a power-on Reset,
RESET# must stay active for at least 1 ms after V
CC and
BCLK have reached their proper specifications. On
observing active RESET#, all FSB agents will deassert
their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is
asserted.
A number of bus signals are sampled at the active-to-
inactive transition of RESET# for power-on configuration.
These configuration options are described in the
Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
3
RS[2:0]# I
RS[2:0]# (Response Status) are driven by the response
agent (the agent responsible for completion of the current
transaction), and must connect the appropriate pins of all
processor FSB agents.
3
RSP# I
RSP# (Response Parity) is driven by the response agent
(the agent responsible for completion of the current
transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to
the appropriate pins of all processor FSB agents.
A correct parity signal is high if an even number of
covered signals are low and low if an odd number of
covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any
agent ensuring correct parity.
3
SKTOCC# O
SKTOCC# (Socket occupied) will be pulled to ground by
the processor to indicate that the processor is present.
There is no connection to the processor silicon for this
signal.
SMI# I
SMI# (System Management Interrupt) is asserted
asynchronously by system logic. On accepting a System
Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor
begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the
processor will tri-state its outputs. See Section 6.1.
2
STPCLK# I
STPCLK# (Stop Clock), when asserted, causes processors
to enter a low power Stop-Grant state. The processor
issues a Stop-Grant Acknowledge transaction, and stops
providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues
to snoop bus transactions and service interrupts while in
Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous
input.
2
Table 4-1. Signal Definitions (Sheet 9 of 11)
Name Type Description Notes