Datasheet

Datasheet 71
Land Listing and Signal Description
MCERR# I/O
MCERR# (Machine Check Error) is asserted to indicate an
unrecoverable error without a bus protocol violation. It
may be driven by all processor FSB agents.
MCERR# assertion conditions are configurable at a
system level. Assertion options are defined by the
following options:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus
transaction after it observes an error.
• Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture,
refer to the Intel
®
64 and IA-32 Architectures Software
Developer’s Manual, Volume 3.
MS_ID[1:0] O
These signals are provided to indicate the Market
Segment for the processor and may be used for future
processor compatibility or for keying. These signals are
not connected to the processor die. Both the bits 0 and 1
are logic 1 and are no connects on the package.
PROCHOT# O
PROCHOT# (Processor Hot) will go active when the
processor’s temperature monitoring sensor detects that
the processor has reached its maximum safe operating
temperature. This indicates that the Thermal Control
Circuit (TCC) has been activated, if enabled. The TCC will
remain active until shortly after the processor deasserts
PROCHOT#. See Section 5.2.3 for more details.
PWRGOOD I
PWRGOOD (Power Good) is an input. The processor
requires this signal to be a clean indication that all
processor clocks and power supplies are stable and within
their specifications. “Clean” implies that the signal will
remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned
on until they come within specification. The signal must
then transition monotonically to a high state. PWRGOOD
can be driven inactive at any time, but clocks and power
must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor;
it is used to protect internal circuits against voltage
sequencing issues. It should be driven high throughout
boundary scan operation.
2
REQ[4:0]# I/O
REQ[4:0]# (Request Command) must connect the
appropriate pins of all processor FSB agents. They are
asserted by the current bus owner to define the currently
active transaction type. These signals are source
synchronous to ADSTB[1:0]#. Refer to the AP[1:0]#
signal description for details on parity checking of these
signals.
3
Table 4-1. Signal Definitions (Sheet 8 of 11)
Name Type Description Notes