Datasheet

Land Listing and Signal Description
68 Datasheet
DBSY# I/O
DBSY# (Data Bus Busy) is asserted by the agent
responsible for driving data on the processor FSB to
indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must
connect the appropriate pins on all processor FSB agents.
3
DEFER# I
DEFER# is asserted by an agent to indicate that a
transaction cannot be ensured in-order completion.
Assertion of DEFER# is normally the responsibility of the
addressed memory or I/O agent. This signal must connect
the appropriate pins of all processor FSB agents.
3
DP[3:0]# I/O
DP[3:0]# (Data Parity) provide parity protection for the
D[63:0]# signals. They are driven by the agent
responsible for driving D[63:0]#, and must connect the
appropriate pins of all processor FSB agents.
3
DRDY# I/O
DRDY# (Data Ready) is asserted by the data driver on
each data transfer, indicating valid data on the data bus.
In a multi-common clock data transfer, DRDY# may be
deasserted to insert idle clocks. This signal must connect
the appropriate pins of all processor FSB agents.
3
DSTBN[3:0]# I/O
Data strobe used to latch in D[63:0]#.
3
DSTBP[3:0]# I/O
Data strobe used to latch in D[63:0]#.
3
Table 4-1. Signal Definitions (Sheet 5 of 11)
Name Type Description Notes
Signals Associated Strobes
D[15:0]#, DBI0# DSTBN0#
D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#
Signals Associated Strobes
D[15:0]#, DBI0# DSTBP0#
D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#