Datasheet

Datasheet 3
Contents
1 Introduction.................................................................................................................9
1.1 Terminology .....................................................................................................10
1.2 References .......................................................................................................12
2 Electrical Specifications ...............................................................................................13
2.1 Front Side Bus and GTLREF ................................................................................13
2.2 Power and Ground Lands....................................................................................13
2.3 Decoupling Guidelines........................................................................................14
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking.......................................15
2.5 Voltage Identification (VID) ................................................................................17
2.6 Reserved, Unused, and Test Signals.....................................................................19
2.7 Front Side Bus Signal Groups..............................................................................20
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals....................................22
2.9 Test Access Port (TAP) Connection.......................................................................22
2.10 Platform Environmental Control Interface (PECI) DC Specifications...........................22
2.11 Mixing Processors..............................................................................................24
2.12 Absolute Maximum and Minimum Ratings.............................................................24
2.13 Processor DC Specifications ................................................................................25
2.14 AGTL+ FSB Specifications...................................................................................32
3 Mechanical Specifications.............................................................................................35
3.1 Package Mechanical Drawings.............................................................................35
3.2 Processor Component Keepout Zones...................................................................39
3.3 Package Loading Specifications ...........................................................................39
3.4 Package Handling Guidelines...............................................................................40
3.5 Package Insertion Specifications..........................................................................40
3.6 Processor Mass Specifications .............................................................................40
3.7 Processor Materials............................................................................................40
3.8 Processor Markings............................................................................................41
3.9 Processor Land Coordinates................................................................................42
4 Land Listing and Signal Description...............................................................................45
4.1 Land Listing......................................................................................................45
4.2 Signal Definitions ..............................................................................................64
5 Thermal Specifications ................................................................................................75
5.1 Package Thermal Specifications...........................................................................75
5.2 Processor Thermal Features................................................................................78
5.3 Platform Environment Control Interface (PECI)......................................................81
6 Features....................................................................................................................85
6.1 Power-On Configuration Options..........................................................................85
6.2 Clock Control and Low Power States ....................................................................85
6.3 Enhanced Intel SpeedStep® Technology ..............................................................89