Datasheet

Datasheet 19
Electrical Specifications
NOTE: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
NOTE: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and
may be used for future processor compatibility or for keying.
2.6 Reserved, Unused, and Test Signals
All Reserved signals must remain unconnected. Connection of these signals to V
CC
, V
TT
,
V
SS
, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs can be left unconnected; however, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TT
). For details see Table 2-18.
TAP, CMOS Asynchronous inputs, and CMOS Asynchronous outputs do not include on-
die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing.
The TESTHI signals must be tied to the processor V
TT
using a matched resistor, where a
matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
The TESTHI signals must use individual pull-up resistors as detailed below. A matched
resistor must be used for each signal:
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12 - cannot be grouped with other TESTHI signals
Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1 LL_ID0 Description
00Reserved
01Intel
®
Core™2 Extreme processor QX9775
10Reserved
11Reserved
Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1 MS_ID0 Description
00Reserved
01Reserved
10Reserved
11Intel
®
Core™2 Extreme processor QX9775