Data Sheet

ManualsBrandsIntel ManualsDevelopment Kit Add-onsDevelopment board 1 pc(s)

Control Description

Address Range (Bytes) Determines the number of addresses to use in each iteration of reads and

writes.

Test Times This item displays test times since you last clicked Start.

Control • Burst Length—Allows you to change the burst length of the design.

Supported burst lengths are 2, 4, 8, 16, 32, 64, and 128.

• Start—Start HyperRAM testing

• Stop—Stop HyperRAM testing

6.6 The Power Monitor

The Power Monitor measures and reports current power information and

communicates with the Intel MAX 10 device on the board through the JTAG bus. A

power monitor circuit attached to the Intel MAX 10 device allows you to measure the

power that the FPGA is consuming.

To start the application, click the Power Monitor icon in the Board Test System

application. You can also run the Power Monitor as a stand-alone application. The

PowerMonitor.exe resides in the <package dir>\examples

\board_test_system directory.

Caution: You cannot run the stand-alone power application and the BTS application at the same

time.

Figure 22. The Power Monitor

6 Board Test System

UG-20082 | 2018.02.05

Intel

Cyclone

10 LP FPGA Evaluation Kit User Guide

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