Data Sheet

ManualsBrandsIntel ManualsDevelopment Kit Add-onsDevelopment board 1 pc(s)

The BTS communicates over the JTAG bus to a test design running in the FPGA. The

BTS and Power Monitor share the JTAG bus with other applications like the Nios II

debugger and the Signal Tap Embedded Logic Analyzer. As the Intel Quartus Prime

uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus

might time-out.

Note: Close other applications before attempting to reconfigure the FPGA using the Intel

Quartus Prime Programmer.

6.1 The Configure Menu

Use the Configure menu to select the design you want to use. Each design example

tests different board features. Choose a design from this menu and the corresponding

tabs become active for testing.

Figure 17. The Configure Menu

To configure the FPGA with a test system design, perform the following steps:

1. On the Configure menu, click the configure command that corresponds to the

functionality you wish to test.

2. In the dialog box that appears, click Configure to download the corresponding

design to the FPGA.

3. When configuration finishes, the design begins running in the FPGA. The

corresponding GUI application tabs that interface with the design are now

enabled.

If you use the Intel Quartus Prime Programmer for configuration, rather than the BTS

GUI, you may need to restart the GUI.

6.2 The System Info Tab

The System Info tab shows the board’s current configuration. The tab displays the

JTAG chain, the board’s MAC address and other details stored on the board.

6 Board Test System

UG-20082 | 2018.02.05

Intel

Cyclone

10 LP FPGA Evaluation Kit User Guide

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