Data Sheet

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Table 25. Flash Memory Map

Block Description Size (KB) Address Comments

Board Test System Scratch 512

0x0073.0000 - 0x007A.FFFF

BTS System Testing

Board Information 64

0x0072.0000 - 0x0072.FFFF

Board Information

Ethernet Option Bits 64

0x0071.0000 - 0x0071.FFFF

MAC Address Information

User Design Reset Vector 64

0x0070.0000 - 0x0070.FFFF

Nios II Reset Vector

Information

Factory Software (ELF) 4096

0x0030.0000 - 0x006F.FFFF

Software File

Factory Hardware (sof) 3072

0x0000.0000 - 0x002F.FFFF

SOF File

Total 7872

The signal connections between the Intel Cyclone 10 LP FPGA and flash comply with

the AS ×1 configuration requirements.

Table 26. Signal Connections

Flash Pin Number Schematic Signal

Name

FPGA Pin Number I/O Standard Description

U2.16

C10_AS_DCLK

U1.H1 3.3 V FPGA Clock Output

U2.7

C10_AS_CSn

U1.D2 3.3 V FPGA Chip Select

Output

U2.8

C10_AS_DATA0

U1.H2 3.3 V FPGA Data Input

U2.15

C10_AS_ASDO

U1.C1 3.3 V FPGA Data and

Control Signals Output

Note: When using a serial flash loader (SFL) core and the Intel Quartus Prime Programmer

to erase and program the flash, virtual JTAG must be bypassed by setting the SW1.4

switch to ON. Signal Net VTAP_BYPASSn is logic 0.

Related Links

Evaluation Board Revisions on page 6

4.11 System Power

4.11.1 Power Supply Options

There are two power supply options provided for the Intel Cyclone 10 LP FPGA

Evaluation Board. The first is USB powered and the second is external AC/DC adapter

powered. These two options can be used for different applications. There is an ORING

circuit on-board to select suitable power source from USB power or DC jack.

USB-Power

A standard A to Mini-B USB Y-Cable is shipped with the evaluation board. There are

three USB ports as listed in the following table.

4 Evaluation Board Components

UG-20082 | 2018.02.05

Intel

Cyclone

10 LP FPGA Evaluation Kit User Guide

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