Data Sheet

Schematic Signal
Name
Schematic
Shared Bus
Signal Name
FPGA Pin Number I/O Standard Direction @ FPGA Description
ENET_RG_TXD3 C10_RG_TXD3
A2 3.3 V Out RGMII TX data 3
ENET_RG_TXCTL C10_RG_TXCTL
D6 3.3 V Out RGMII TX control
ENET_RG_RXCLK RG_RXCLK
B8 3.3 V In RGMII RX Clock
ENET_RG_RXD0 RG_RXD0
A7 3.3 V In RGMII RX data 0
ENET_RG_RXD1 RG_RXD1
B7 3.3 V In RGMII RX data 1
ENET_RG_RXD2 RG_RXD2
A6 3.3 V In RGMII RX data 2
ENET_EG_RXD3 RG_RXD3
B6 3.3 V In RGMII RX data 3
ENET_RG_RXCTL RG_RXCTL
A5 3.3 V In RGMII RX Control
ENET_INT
B5 3.3 V In Management
Interrupt
ENET_MDC
B4 3.3 V Out MDIO clock
ENET_MDIO
A4 3.3 V I/O MDIO data
ENET_RSTn
C6 3.3 V Out Device Reset
ENET_XTAL1
ENET_XTAL2
ENET_LED0
3.3 V Out Status LED0,
Green
ENET_LED1
3.3 V Out Status LED1,
Green
ENET_LED2
3.3 V Out Status LED2,
Green
TPIAP
Twisted-Pair A,
positive
TPIAN
Twisted-Pair A,
negative
TPIBP
Twisted-Pair B,
positive
TPIBN
Twisted-Pair B,
negative
TPICP
Twisted-Pair C,
positive
TPICN
Twisted-Pair C,
negative
TPIDP
Twisted-Pair D,
positive
TPIDN
Twisted-Pair D,
negative
Note: 10/100/1000 Ethernet is supported beginning with the Intel Quartus Prime v17.1
software release.
4 Evaluation Board Components
UG-20082 | 2018.02.05
Intel
®
Cyclone
®
10 LP FPGA Evaluation Kit User Guide
24
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