Data Sheet

Figure 6. Intel Cyclone 10 LP FPGA Clock Tree
Cypress CY7C68013A
USB Controller
Cyclone 10 LP
8 7
3 4
2 1 5 6
MAX 10
On-Board Intel® FPGA
Download Cable II
C10_CLK50M
Si50 50 MHz
Oscillator
24 MHz
Crystal
USB_CLK
M10_CLK50M
Default LVCMOS 125 MHz
25 MHz
Crystal
Default LVCMOS 50 MHz
LVCMOS Adjustable
Si5351
ENET_CLK_125M
HBUS_CLK_50M
C10_CLK_ADJ
4.9 Connectors and Interfaces
This section describes the evaluation board's communication ports, and interface cards
related to the Intel Cyclone 10 LP FPGA Evaluation Kit.
4.9.1 Gigabit Ethernet PHY
The evaluation board supports single port Ethernet through Intel XWAY PHY11G
PEF7071 Ethernet PHY chips. This physical layer device has general applications using
RJ-45 connector.
Figure 7. MAC-to-PHY connection by PEF7071 device
Specific to the Intel Cyclone 10 LP FPGA evaluation board, the MAC-to-PHY interface is
configured to a RGMII interface connection with MDIO interface as management.
Table 14. Ethernet PHY Table
Schematic Signal
Name
Schematic
Shared Bus
Signal Name
FPGA Pin Number I/O Standard Direction @ FPGA Description
ENET_RG_TXCLK C10_RG_TXCLK
D3 3.3 V Out RGMII TX clock
ENET_RG_TXD0 C10_RG_TXD0
E6 3.3 V Out RGMII TX data 0
ENET_RG_TXD1 C10_RG_TXD1
A3 3.3 V Out RGMII TX data 1
ENET_RG_TXD2 C10_RG_TXD2
B3 3.3 V Out RGMII TX data 2
continued...
4 Evaluation Board Components
UG-20082 | 2018.02.05
Intel
®
Cyclone
®
10 LP FPGA Evaluation Kit User Guide
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