Data Sheet

4.7 General User Input/Output
Table 11. DIP Switches
Board Reference Schematic Signal
Name
FPGA Signal Name Description
SW1.3
USER_DIP0 U1.M16
User-defined Switch0
SW1.2
USER_DIP1 U1.A8
User-defined Switch1
SW1.1
USER_DIP2 U1.A9
User-defined Switch2
Table 12. Push Buttons
Board Reference Schematic Signal
Name
FPGA Signal Name Description
S3
USER_PB0 U1.E15
User-defined PB0
S4
USER_PB1 U1.F14
User-defined PB1
S5
USER_PB2 U1.C11
User-defined PB2
S6
USER_PB3 U1.D9
User-defined PB3
Table 13. LEDs
Board Reference Schematic Signal
Name
FPGA Signal Name Color Description
D6
USER_LED0 U1.L14
Green User-defined LED0, active low
D7
USER_LED1 U1.K15
Green User-defined LED1, active low
D8
USER_LED2 U1.J14
Green User-defined LED2, active low
D9
USER_LED3 U1.J13
Green User-defined LED3, active low
4.8 Clocks
Si5351 is a programmable clock generator that users can use Intel Clock GUI to
program output frequency. It is controlled from Intel MAX 10 with I
2
C bus.
The clock tree is shown in the figure below.
4 Evaluation Board Components
UG-20082 | 2018.02.05
Intel
®
Cyclone
®
10 LP FPGA Evaluation Kit User Guide
22
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